Primetime set constraints problem

Hello,

i want to do a power analysis on the post-synthesis netlist of my design.

My main design inputs are connected with one of my sub-designs inputs(i.e. with the component's A inputs).
My main design outputs are connected with one of my sub-designs outputs(i.e. with the component's B inputs).

Here is the problem:

When i set constraints for my main design inputs these constraints do not apply to my component's A inputs .
Specifically i use the command set_drive value [all_inputs].

Same case with the outputs: When i set constraints for my main design outputs these constraints do not apply to my component's B outputs.
Specifically i use the command set_load value [all_outputs].

Any ideas why this may happen?As i see in my netlist vhdl code the inputs of my main design and the component's A and the outputs of my main design and the component's B are connected without any logic between them.

The problem is also that i can set these constraints only to the primary inputs/outputs of my design and not to the inputs/outputs of sub-designs...Is there any way to set these directly to the inputs/outputs of my sub-designs A and B ?

Thank you in advance.