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VHDL problem: NUMERIC_STD.">": metavalue detected, returning FALSE

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Hi everybody. I'm have to implement a testbench for a sign-mag adder in a college project, but im having problems.
I can do the analysis and the elaboration without any problems, however when i try to execute the files i receive the message
"../../src/ieee/numeric_std-body.v93:1005:7:mad:0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE"
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Im new to vhdl, so i don't have any idea how to solve it.
 
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Re: VHDL problem: NUMERIC_STD.">": metavalue detected, returning FALSE

The assertion is triggered by a X (unknown) value in one of the inputs to ">" (GREATER) comparison.

Find out where the X value comes from. Most simulators have tools to trace the source of unknown values, review the user manual.
 

Re: VHDL problem: NUMERIC_STD.">": metavalue detected, returning FALSE

It will be triggered by any comparison where one of the values contains any non binary ('0' or '1') value, not just 'X'. all 'U' is a prime trigger for this (ie. before reset occurs).
 

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