Error while simulating the system verilog code using questasim 10.5 version

//COUNTER DESIGN

//D FLIPFLOP
module dff(clk,reset,din,dout);
input clk,reset,din;
output dout;
logic dout;

always@(posedge clk,negedge reset)
if(!reset)
dout <= 0;
else
dout <= din;
endmodule

//COUNTER
module ones_counter(clk,reset,data,count);
input clk,reset,data;
output [0:3] count;

dff d1(clk,reset,data,count[0]);
dff d2(count[0],reset,~count[1],count[1]);
dff d3(count[1],reset,~count[2],count[2]);
dff d4(count[2],reset,~count[3],count[3]);

endmodule

//INTERFACE
interface intf_cnt(input clk);

//wire clk;
wire reset;
wire data;
wire [0:3] count;

endinterface


//STIMULUS :: TRANSACTION ITEM
class stimulus;
rand bit value;
constraint distribution {value dist { 0 := 1 , 1 := 1 }; }
endclass 

//SCOREBOARD
class scoreboard;
bit [0:3] store;
endclass 


//DRIVER
class driver;
stimulus sti;
scoreboard sb;

covergroup cov;
Feature_1: coverpoint sb.store ;
Feature_2 : coverpoint sb.store { bins trans = ( 15 => 0) ;}
endgroup

virtual intf_cnt intf;

function new(virtual intf_cnt intf,scoreboard sb);
this.intf = intf;
this.sb = sb;
cov = new();
endfunction

task reset(); // Reset method
intf.data = 0;
@ (negedge intf.clk);
intf.reset = 1;
@ (negedge intf.clk);
intf.reset = 0;
@ (negedge intf.clk);
intf.reset = 1;
endtask

task drive(input integer iteration);
repeat(iteration)
begin

sti = new();
@ (negedge intf.clk);
if(sti.randomize()) // Generate stimulus
intf.data = sti.value; // Drive to DUT
sb.store = sb.store + sti.value;// Cal exp value and store in Scoreboard
if(sti.value)
cov.sample();
end
endtask
endclass

//MONITOR
class monitor;
scoreboard sb;
virtual intf_cnt intf;

function new(virtual intf_cnt intf,scoreboard sb);
this.intf = intf;
this.sb = sb;
endfunction

task check();
forever
@ (negedge intf.clk)
if(sb.store != intf.count) // Get expected value from scoreboard and compare with DUT output
$display(" * ERROR * DUT count is %b :: SB count is %b ", intf.count,sb.store );
else
$display(" DUT count is %b :: SB count is %b ", intf.count,sb.store );
endtask
endclass 

//ASSERTION
module assertion_cov(intf_cnt intf);
Feature_3 : cover property (@(posedge intf.clk) (intf.count !=0) |-> intf.reset == 0 );
endmodule 



//ENVIRONMENT
class environment;
driver drvr;
scoreboard sb;
monitor mntr;
virtual intf_cnt intf;

function new(virtual intf_cnt intf);
this.intf = intf;
sb = new();
drvr = new(intf,sb);
mntr = new(intf,sb);
fork
mntr.check();
join_none
endfunction

endclass 



module top1();
reg clk = 0;
initial // clock generator
forever #5 clk = ~clk;

// DUT/assertion monitor/testcase instances
intf_cnt intf(clk);
ones_counter DUT(clk,intf.reset,intf.data,intf.count);
testcase test(intf);
assertion_cov acov(intf);
endmodule

//TEST
program testcase(intf_cnt intf);
environment env = new(intf);

initial
begin
env.drvr.reset();
env.drvr.drive(10);
end
endprogram

module assertion_cov(intf_cnt intf);
Feature_3 : cover property (@(posedge intf.clk) (intf.count !=0) |-> intf.reset == 0 );
endmodule