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  1. #1
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    How to infer flip-flops from CLBs?

    hi

    I am trying to infer 128 bit register in spartan-3 FPGA. when i implement the design i get error during the mapping stage " The design is too large for the given device and package."

    it is mapping the flipflops to iobs and the package xc3s200 doesnt have enough iobs .

    is there any way i can infer flipflops from clbs?

    your help is highly appreciated.

    thanks

    sriram

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  2. #2
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    Re: inferring FF in CLB

    Don't use the module with the 128-bit output as a top level module.



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  3. #3
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    inferring FF in CLB

    All the synthesis tools can infer the FFs from the CLB.

    Rgds,
    zcq



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    Re: inferring FF in CLB

    Show us your code.

    What software are you using?

    This implemented just fine in a 3s50-vq100 using ISE XST. It created a large register and one output IOB, as I expected:
    Code:
    module top(clk, out);
      input             clk;
      reg       [127:0] count = 0;
      output            out;
    
      assign out = count[127];
    
      always @ (posedge clk) begin
        count <= count + 1;
      end
    endmodule



  5. #5
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    Re: inferring FF in CLB

    But if the output of the 128-bit register is part of the interface (port in VHDL), synthesis will work, but implementation may try to move the register to the IOBs.

    It doesn't really matter if the FFs are in CLBs or IOBs. If all 128 output bits are being connected to IO pins, and your package is too small, you get the "design is too large" error message.



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    Re: inferring FF in CLB

    Disable the IOB fitting in settings.



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  7. #7
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    inferring FF in CLB

    I agree to what tkbits says
    It doesn't really matter if the FFs are in CLBs or IOBs. If all 128 output bits are being connected to IO pins, and your package is too small, you get the "design is too large" error message.
    If u r having more number of outputs than what are available, error message will come.

    Anyways, IOB fitting can be changed by (in XILINX ISE):
    1. Right Click on MAP in Implement Design (in Process Window)
    2. Select Properties
    3. Turn off Pack I/O Registers/Latches into IOBs option.



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