Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Moved]: Mismatch between expected and simulated patterns in scan serial

Status
Not open for further replies.

chaitanyavarma007

Newbie level 3
Joined
Mar 25, 2016
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
20
Hi,
I was performing simulation(scan_serial) in synopsys vcs for one block named rx_pd after performing pattern retargetting.
I got an error saying that Mismatch occurred
Signal name: SEL_VAUX_B
timestamp : 31290ns
instance : topmodule/submodule/core/edt_rx_pd_channel2
Simulated : x
Expected : 1
The signal is found in topmodule,but its value is x in submodule and core.
How to resolve it?
 

Read simulation log and find the violation line
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top