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of course, I look at the footprint. It has a thermal pad under the chip. There is no any description about the it. What I can guess is the thermal pad is the GND pin. But it is just my guess.
Apparently Lattice managed to hide the information perfectly in the ICE40 datasheet...
For me it's quite obvious that the exposed pad is acting as ground, same thing with some Altera CPLD and FPGA. But you can ask at Latticesemi where it's written explicitly.
"One tricky thing about QFNs ( also known as MLFs ) is the substrate ground slug in the center. For many devices – it is the only ground connection and must be soldered – so I place a 0.125″ hole underneath the slug."
"One tricky thing about QFNs ( also known as MLFs ) is the substrate ground slug in the center. For many devices – it is the only ground connection and must be soldered – so I place a 0.125″ hole underneath the slug."
Actually, it is mentioned in the datasheet, but it is very well hidden. Took me quite some time to notice it. In "iCE40UltraFamilyDataSheet.pdf", right under table "Pin Information Summary", there is a note. It reads: "48-pin QFN package (SG48) requires the package paddle to be connected to GND."
It's the only part of the documentation that cleared this up. I think it should be a lot more visible.
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