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inductance of the metal layers in the layout is not included in parasitic extraction....Why not considering ? even the chip is working at high frequency?
I think inductance will come in picture when metal winding is more , meance round shape metal for ex. M1 to M5.
In layout will draw metal as straight for routing purpose, there inductance is negligible.
During the Parasitic Extraction, you have to opt for the Inductance extraction also. R u doing that part ?
Second thing what type of design you have have.. If it's Digital - I don't think you will get Inductance.
you should do hand calculations to see how much inductance is there between to wires in a design( any standard physics book will have the method). It will be very small. The only place where inductance is extracted when the designer is actually try to make an inductor for RF applications. These are special inductor layout guidelines provided by the foundry.
Finally I got the answer, Inductance will come into picture when width of the interconnect is more or frequency is high.
Z=R+Lw (Impedance of the interconnect/net).
R= resistance
L= inductance
w= frequency
scenario 1 ) when frequency is more inductance part dominates.
scenario 2 ) when width increases resistance decreases, it will dominates inductance terms.
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