Low power and UPF for low power

[sun_ray]

There are commands in upf to place switching fabric for power gating. Is it that this UPF can only be included during RTL synthesis and the netlist generated will have the switching fabric which cuts or supply the power whenever necessary?

Is there any way to include low power things like switching fabric to be incorporated in the RTL level or any other stage of digital design cycle other that RTL synthesis.

Regards

[kvingle]

Is there any way to include low power things like switching fabric to be incorporated in the RTL level or any other stage of digital design cycle other that RTL synthesis.

Regards

UPF => Unified Power Format. The reason its called this is, its intended to use across all the chip flow i.e. from RTL to layout.

The UPF used in synthesis is used for RTL simulation as well. However in layout UPF generated from synthesis tool is used because it has more information about the low power related cells and their hierarchy.

[sun_ray]

UPF => Unified Power Format. The reason its called this is, its intended to use across all the chip flow i.e. from RTL to layout.

The UPF used in synthesis is used for RTL simulation as well. However in layout UPF generated from synthesis tool is used because it has more information about the low power related cells and their hierarchy.

At what stage in the digital design cycle are the low power things like switching network are inserted in the netlist? Is it duing RTL synthesis only or any other stage in the digital design cycle? Is it only inserted in the netlist using UPF or it is also inserted in some other way also?

Regards

[dpaul]

In most cases it is done by the synthesis tool before writing out the final netlist.
Till now I have not come across your "low power things" (nice term ) at the RTL level.
Regarding how exactly it is inserted, a synthesis expert can tell you.

[kvingle]

Till now I have not come across your "low power things" (nice term ) at the RTL level.

In RTL there is no low power specific gates (such as power gates, isolation/retention cells etc) available. But power aware simulators are able to understand the missing hardware components after reading power intent file and include 'virtual' cells in place of 'expected' hardware. To make it more clear, say you have specified a isolation to inputs of domain A in your UPF but as isolation cells be inserted only after synthesis, 'power aware 'simulators includes virtual cells in simulation which can act as real hardware.

At what stage in the digital design cycle are the low power things like switching network are inserted in the netlist? Is it duing RTL synthesis only or any other stage in the digital design cycle?

Regards

Isolation cells are inserted in synth.
power gates in layout.

Is it only inserted in the netlist using UPF or it is also inserted in some other way also?

Even before UPF/CPF came into mainstream low power designs were made. In those days(even now in some projects) these low power cells are coded in rtl or inserted during synth/lay stages.

I used to add isolation cells in rtl few years back.

Hope this helps.

[sun_ray]

In RTL there is no low power specific gates (such as power gates, isolation/retention cells etc) available. But power aware simulators are able to understand the missing hardware components after reading power intent file and include 'virtual' cells in place of 'expected' hardware. To make it more clear, say you have specified a isolation to inputs of domain A in your UPF but as isolation cells be inserted only after synthesis, 'power aware 'simulators includes virtual cells in simulation which can act as real hardware.




Isolation cells are inserted in synth.
power gates in layout.



Even before UPF/CPF came into mainstream low power designs were made. In those days(even now in some projects) these low power cells are coded in rtl or inserted during synth/lay stages.

I used to add isolation cells in rtl few years back.

Hope this helps.

At what stage does the switching fabric inserted in the netlist and how?

What do you mean by power gates?

What do you mean by layout level. Is it placement stage or at routing stage? How are low power things are inserted in the netlist in layout stage?

[kvingle]

A low power design is characterized by different power domain which can be switched on/off using 'power gate transistor' which acts as switch for power supply rail. Switching fabric is not suitable term here.
Power gates are inserted during 'placement' stage.

[sun_ray]

A low power design is characterized by different power domain which can be switched on/off using 'power gate transistor' which acts as switch for power supply rail. Switching fabric is not suitable term here.
Power gates are inserted during 'placement' stage.

Are not the power gates inserted in RTL synthesis stage?

How are these power gates inserted during placement? Is it that they are inserted using UPF? Is it that UPF automatically insert the transistors for power gates during placement?

[kvingle]

Are not the power gates inserted in RTL synthesis stage?

No, as mentioned earlier.

How are these power gates inserted during placement? Is it that they are inserted using UPF? Is it that UPF automatically insert the transistors for power gates during placement?

Tools supporting low power + UPF do it automatically.

[sun_ray]

Can you please name some tools which insert power gates? Is it Synopsys ICC one of them?

Is it that level shifters and isolation cells are all inserted during RTL synthesis only? Can the level shifters and isolation cells be inserted in other stage like placement & routing other than rtl synthesis?

[kvingle]

Can you please name some tools which insert power gates? Is it Synopsys ICC one of them?

Yes. Nowadays all PnR tools support UPF flows.

Is it that level shifters and isolation cells are all inserted during RTL synthesis only? Can the level shifters and isolation cells be inserted in other stage like placement & routing other than rtl synthesis?

Yes, you can insert them later stages at well. Level shifters are usually added during placement.

[sun_ray]

Yes. Nowadays all PnR tools support UPF flows.


Yes, you can insert them later stages at well. Level shifters are usually added during placement.

What are normally the digital design cycle stages where low power things are inserted in the design? Can you please list down a table where it will show the low power things that are inserted in integrated circuits and the corresponding stages in digital design cycles where they are inserted normally and also what are the other stages in digital design cycle they can be inserted other than the stage where they are inserted normally? You may make three columns in that table with column 1 containing low power things that are inserted in integrated circuits , column 2 containing corresponding stages in digital design cycles where they are inserted normally, column 3 containing the other stages in digital design cycle they can be inserted other than the stage where they are inserted normally?