Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Constant precision frequency generator?

Status
Not open for further replies.

psoc77

Junior Member level 1
Joined
Feb 5, 2016
Messages
17
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,283
Activity points
1,388
Hi,
I am looking for method of constant precision frequency generation in audio range 20Hz - 20kHz with precision dF/F ~ 1E-3. For example, for the set frequency 20kHz, the output should be in range 20'000+/-20 Hz, and for set frequency 20Hz, the output should be within range 20+/-0.02Hz. Can you advise on what approach should I use?

To exemplify the problem, using PWM, precision increases as dF/F ~ F - good for low frequency, not so much for high one. With DDS, precision behaves like dF/F ~ 1/F (good for high frequency).

Q: how to get constant accuracy over entire range: dF/F ~ const?
 

Last edited:

Tony,
Thank you for reply, but I am familiar with DDS. In this simple case 20-20'000 Hz, to get 1E-4 precision we need 32-bit DDS already.

I hope there are other known solutions, as I don't want to invent a bicycle.
 

1e-3 is not really a high precision. Conventional analog circuits can do the job if you pay attention to (i) regulate well the supply voltage (ii) regulate the temperature (iii) age the components (whatever that may mean).

We had a HP function generator that had a jumbo dial and a range switch. We connected a speaker to the output and check the frequency with a tuning fork! The good old days.
 

c_mitra,
I would like to implement it with uC or FPGA, and was thinking that there is some well-known solution, as problem seems very common.
 

Using uC or other digital techniques, you can get highly stable frequencies (in NMR and ESR we need frequencies that are stable to 0.01Hz at 500 MHz) but they will not be continuously variable.
 

c_mitra,
Thank you for reply, it kinda reminded me the the old days, when I was actually doing ESR and NMR work. Now I am a hobbyist trying to understand how uC works and how to produce with it accurate tones with same precision over the large span. Some keywords may be helpful to stirr me in right direction.
 

Hi,

As said before, I also agree that a DDS is what you need.

And for a 10E-3 frequency resolution .... why do you think you need 32 bits?
For the NCO you need 14 bits for the 10E-4... and extra 10bits for the 20Hz to 20kHz range.
It makes at least 24 bits....with 26..28 bits you should be on the save side. (For sure you need to adjust the range)
(But even 32 bits should be no problem when you build it in an FPGA, the NCO is mainly a simple adder)

Do you have additional requirements regarding THD or so?

Klaus
 

KlausST,
I have DDS programmed into FPGA, but was quite disappointed that it's relative accuracy drops at low frequencies as ~const/F. You have to add ~8bit on top of high frequency range to avoid phase jitter, which brings 24 bits you have calculated to 32 bits.

Again, my question is rather theoretical. Lacking background in electronics I just want to understand if any standard approach to this problem exists.
 

Hi,

One can see it as a benefit, that the DDS has a constant frequency resolution. But for audio maybe a logarithmic solution has it´s improvements.

With a constant delta-f stepsize, you have absolute resolution. No relative reolution. This is a drawback at low frequencies.
But accuracy is different. The accuracy should be very cloase to +/- 1/2 LSB.
And the precision should be far better.

For sure it generates phase jitter. But i think (I´m not sure of) the jtter mainly depends on NCO input frequency, and not that much on NCO resolution. It also depends on sine lookup table resolution.. and if you use some interpolation between phase values in the lookup table.
You could improve phase jitter to certain frequencies, if there are any of special interest. Just try meet exactely the phase steps of the table at those frequencies.

****
besides DDS which uses the NCO with it´s drawback..
you could use a high frequency source and use integer dividers to get your DAC sampling frequency. And use a fixed table with the sine values.
The divider method has improvents in frequency resolution at lower frequencies. (n steps per octave)

You need a DAC that can operate with varying sample frequency.

Instead of the integer divider you coud use an external adjustable PLL (often FPGA inside PLLs are difficult to configure on the fly),
or try to implement a DLL (I think it operates similar to an NCO, so first check if this is really an improvement against DDS).

Klaus
 

You have to add ~8bit on top of high frequency range to avoid phase jitter, which brings 24 bits you have calculated to 32 bits.
Sounds like a misunderstanding of DDS principle. You can get pretty low jitter after the DDS output filter with a carrier fulfilling the Nyquist criterion, achieving low jitter is much more a problem of sufficient DAC resolution. Consider that DDS is often used to generate a continuously frequency variable digital clock, without much carrier frequency overhead, a way of trading magnitude resolution against phase resolution.

I don't see what's the problem in making a 32 bit or even wider DDS generator, particularly in a FPGA design. DDS is clearly the standard solution you are asking for.
 

I know what is PLL, but what is DLL stands for?
 

What is "logarithmic solution"?
 

Hi,

I know what is PLL, but what is DLL stands for?
I meant DPLL, a fully digital PLL solution.

What is "logarithmic solution"?
with a NCO the stepsize is constant.
Maybe you have a stepsize of 1Hz, then you could generate 20Hz, 21Hz, 22Hz...so from 20Hz to 21 Hz there is a deviation of 5%
But you could generate 20000Hz, 20001Hz, 20002Hz.. the deviation from 20000Hz to 20001 Hz is only 0.005%

With logarithmic I meant how the musical scale is made. 440Hz is an A.. the next A is at 880Hz, the next is at 1760Hz...
So if you draw frequencies of the "A"s (or any other notes) of different ocatves in a logarithmic scale then they have equal distance.
From G to A in different octaves there is not a fixed frequency step size, but a fixed % step size.

The same is with the E-series of resistors.

****
Correct me if I´m wrong.
To me it seems you rather need a constant "percentage" step size than a fixed frequency step size.

Klaus
 

KlausST,
Thank you for reply.

Hi,

Correct me if I´m wrong.
To me it seems you rather need a constant "percentage" step size than a fixed frequency step size.

Klaus

Exactly, to have dF/F = const, dF has to be proportional to F.


From the feedback I get feeling that there is no established solution, which may justify developing my own. I have no application in mind, this is just "theoretical" exercise which I want implement in Verilog.
 

You didn't yet tell what you expect from your own solution compared to a "wide" DDS design, except for saving a few logic cells in the DDS logic (and possibly spending the tenfold amount in a different place). Maximum jitter will be set by the system clock period, or you need analog PLLs to generate a continuously variable clock. And frequency resolution is just a matter of word width.

It's a different point to possibly use a logarithmic or whatsoever scaling for the frequency control word, but it doesn't change the above mentioned parameters of signal generation.
 

Yes, we need to start with 1 and keep on multiplying with 1.001 and wait till you reach 10. Multiply the series with 10 and get the next series for 10 to 100. Each series will have 2303 members (like the E96 series). Now you will have 10-100, 100-1000, 1000-10000, 10000-100000 - four series each with 2000 numbers. All these will be within 0.1% of each other. They will be discrete steps but will look linear on a log scale...
 

Actually, I am thinking of sequential combo PWM-DDS, e.g. PWM feeding the sampling clock of DDS. If for PWM dF/F ~ F, and for DDS dF/F ~ 1/F, then overall precision of the system will be
dF/F ~ F * (1/F) = const. Question is how to divide frequency between PWM and DDS optimal way.
 

I presume, the term "pwm" in this regard has nothing to do with pulse width modulation but simply describes a programmable frequency divider.

I agree that a frequency divider can help to reduce the DDS width while keeping a certain relative resolution. Most likely, a binary prescaler would be sufficient. But it's a bad idea related to the analog outside because it requires to switch the anti-aliasing output filter together with the divider steps.

And as asked before, where's the actual advantage?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top