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Trace Spacing in high speed PCB DDR3L routing

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ibrahimNazir

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Hi,

I am working on high-speed PCB and I am new in this field. According to design routing guide I need to know what is trace 3x units Dielectric actually means
It is spacing from other signals but I am confused in 3x

Please se the attached photo
eda.JPG
 

To reduce crosstalk track space to width ratio 3x is suggested here, but this assumes a ground plane.

50 ohm tracks are approx equal to dielectric thickness and approx. match CMOS driver impedance on most but not all LV logic.
 

means if you are routing 1mm 50ohm track then spacing between next signal track is about greater or equal to 3mm.
 

Run clocks 3X from any other traces, generally you will only have space to route at 0.1mm/0.1mm, this is usual for todays dense high speed boards.
Use a PCB impedance calculator such as Saturn toolkit to determine the characteristic trace impedance....
With DDR interfaces you will very lucky if you have the room to route with a space of 3X the trace width, 1X is more likely.... Route the data lanes on different layers to the address and control signal. Micron has many guides for routing DDR interfaces I would suggest you go read them as well as other guides.
 

Also read JEDEC standard JESD79-3F. This has lots of information. If you got login with JEDEC then download their sample layout examples. Another important thing you should check if your uC supports 'Write Levelling' to connect DDR3.
 

If I understand right, 3 x dielectric means what it says: 3 times the microstrip substrate height.
 

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