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    question regarding timing analysis

    Hi All,

    If ur data path is optimized ( 2 flops and a combo logic) and have setup violation,what option you use to fix setup violation ?

    Could u answer this ?

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    Re: question regarding timing analysis

    Try to look at the formula of setup timing slack, you can see which are possible factor to change in order to clear the negative slack.


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    Re: question regarding timing analysis

    Reduce data path delay by using repeaters or intermediate buffers.



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    Re: question regarding timing analysis

    Hi,

    If there are huge setup violations ,we have methods to fix ,what are the methods to fix huge hold violations (exclusively in primetime ) apart from manual fixing techniques ?



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    Re: question regarding timing analysis

    You can work on the skew (push the clock) after looking at the slack on the other side.
    There are certain flops with different library setup time. You can swap them accordingly.



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    Re: question regarding timing analysis

    hi

    larger skew is negative for hold fixes,so can i really work on skew ?



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    Re: question regarding timing analysis

    Quote Originally Posted by cyrax747 View Post
    Hi,

    If there are huge setup violations ,we have methods to fix ,what are the methods to fix huge hold violations (exclusively in primetime ) apart from manual fixing techniques ?
    You can use the automated solution in primetime, prime time ECO solution for fixing hold violations. either by swapping to higher vt cells or by adding buffers.
    If you want to re-design and fix the issues by correct by construct, then you might need to add tighter skew constraint and balance the clocks properly with tighter constraint. Use scan chain re-ordering technique to minimise the cross domain clock paths which minimises the scan related hold violation. Use the flip flop cells which separate sq pin as it has internal hold padding. try to put clock transition constraint during CTS so that we have faster slews at the flop inputs and resulting lesser hold requirement.


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    Re: question regarding timing analysis

    I am not sure when you are saking this question - At what stage are you .. Like Pre-CTS or Post Routing.
    Solution can be little bit vary in both the case. As such remember - there is no set of rules which you can follow to Fix the Setup violations. Solution depends on the problem and the constraints of the path.
    You have to understand that Setup is because of Maximum path Delay > certain value .. so you have to reduce this Delay.

    When you are saying that path is optimized, I am assuming that you can't make any change in the type of gates you have used. If that's true - you can see if you can play with the internal Delay table of the Gate.. Means try to change the input Transition time or Output Load. It can help you to reduce the max delay of corresponding gate and may solve your problem. This thing you can do by re-positioning the gate between 2 Flipflops.

    There are several other ways also. This place is very short to explain all those - I will suggest read good articles on that for more understanding.

    I recommend - www.vlsi-expert.com
    -Vlsi Expert



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