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Why the threshold voltage of MOS decreases as channel length increases?

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anhnha

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I am wondering why the threshold voltage of MOS decreases as channel length increases. Could anyone explain this?
 

threshold voltage decreases as channel length decreases. For a long channel device, the depletion layer thickness at the source end of the channel and at the drain end of the channel are much less than the channel length L, and, thus, the depletion charge enclosed by these sections are much smaller than the total depletion charge under the gate.
However, for a short channel device, the widths of these depletion regions are a non-negligible fraction of the total depletion charge under the gate.
Note: essentially, the depletion regions near the source and the drain are contributed by the source-substrate and the drain-substrate bias, and gate has no role to play.
Under an applied drain-source bias, the depletion region thickness near the drain will obviously be larger than that at the source side.
The net effect is that the gate now has to compensate for a lower depletion charge density than that for a long channel device, which qualitatively explains the reduction of the threshold voltage with a reduction in the channel length.
 

"Reverse short channel effect" is now a thing. Used to be
that VT would reduce w/ L due to short channel effects,
drain field summing w/ gate field. But modern technolgies
are not much like what you are shown in school for a
classical MOSFET - multiple implants (halo, LDD) and
these are tuned for the bleeding edge leaving the long
channel "analog" stuff to fall where it may - higher or
lower, because digital is the reason for existence and
must be coddled. At any rate the channel is now in a
bed of various pinches and gradients and nothing can
be assumed about how device IV curves match up to
classical or even neo-classical expectations.
 

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