Pins on the Zynq FPGA

Hello,

I have one very basic question. Can we use the MIO and EMIO pins and dedicate them for any modules of our choice (UART, SPI, I2C)? Is it just that we have to write codes for the interface modules by utilizing any pins and make it work as per our needs? Also if i need 3 to 4 UARTs on the PS, is it possible? I may not use CAN and USB which is available. Please confirm.

For the peripherals (UART, SPI, I2C, CAN, USB, ...) that are part of Zynq micro-controller (part of PS) you can select if peripherals pins are MIO or EMIO. MIO pins are predefined, you can pick pins from predefined sets of possible pin connections for the particular PS peripheral. If you run Vivado or PlanAhead Zynq configuration, the tools will guide you through valid selections from MIO pins sets for selected peripheral (e.g. selecting SPI0 will show you possible MIO connections). If you select EMIO to be pins for PS peripheral, than you will have to define where you want those pins to be located in the constraint (XDC) file with PACKAGE_PIN property and connect them in your top HDL module with Xilinx tools generated system (PS module) wrapper module. There are Xilinx howto docs describing much better than I can, the process of using EMIO pins. Just search and read them. One substantial difference between using MIO or EMIO pins is that, if you chose EMIO pins for PS peripheral, than PL must be configured (FPGA design running) to have pins connected to the PS peripheral (they are wires through PL logic). E.g. Linux device driver (e.g. for UART you have configured to use EMIO) can use that PS UART device only if PL is configured (wire connection through PL logic must exist). On the other hand, MIO pin PS peripheral connections does not require PL to be configured, pins are connected outside PL via PS configuration registers set up by FSBL.

The number of Zynq PS peripherals is fixed, e.g. there are 2 UARTs. If you need more than 2 UARTs, you will have to code them in PL, by write HDL logic and connect it to some (not MIO) pins. If you code your own HDL logic for UART, than you must think also how will your SW (or end customer SW) use them. Usually (but not necessary) in Linux, this is done by writing device driver.