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porting of constraints for synthesis at the top?

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sun_ray

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Suppose I have constraints for five blocks for the synthesis of each of the five blocks. Now this five blocks are instantiated at a top level module and I want to synthesize this top level module. How should we proceed? How can we port the constraints of these five blocks at the top?
 

You might have to change the port names in the constraints. Replace the port names of the inner modules with the port names of the top module. You will also need to change the hierarchies within the constraints.
 

What kind of constraints are these? Are they placement? pinout? timing constraints?

Pin constraints will need to be set up for your new top level. Other constraints will need modifying to reflect the new heirarchy structure.
 

if they are SDC timing constraints, they all you need to ensure is that the paths are correct based on the new heirarchy. Usually putting wildcards at the front will probably do it.
 

Is there any general way of porting constraints from the sub modules to top level?
 

Yeah, it's called opening a text editor with the code in one window, the constraints files in another window, and the new constraints file in a third window. Then doing cut and paste between the old constraints files and the new top level one, changing the names of the signals in the new file as you go through the old files.:roll:
 

We all are aware of this solution. So this solution does not help. Can anybody provide any better solution known to port ?
 

I really dont know what more you are asking for.
You just collate the constraints you already have into a single file.
 

sun_ray said:
We all are aware of this solution. So this solution does not help. Can anybody provide any better solution known to port ?
Click to expand...

Then write a script in Perl/Tcl/Python/Favorite_srcipting_language to automate it.

I'm done...new addition to the ignore list.
 

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