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2 stage op amp with PMOS inputs.

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sherlock176

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for gpdk180nm uncox=400u and upcox=70u
Vtn= 470mV and Vtp=450mv

Please guide me through calculations for how to design of 2 stage opamp with specs as

Vdd=1.8V, Cc=800fF, Gain = 50-60dB?
 

If you have no specs of min. bandwidth / max. power consumption, you could follow this Jespers MOS-AK workshop example, slides 41 .. 51.

Your threshold data aren't used in this gm-over-Id methodology run, however. These could slightly change the received values in the real design.
 

sherlock176 said:
for gpdk180nm uncox=400u and upcox=70u
Vtn= 470mV and Vtp=450mv

Please guide me through calculations for how to design of 2 stage opamp with specs as

Vdd=1.8V, Cc=800fF, Gain = 50-60dB?
Click to expand...

I think that with 1-2 page, it's hard to explain and guide designing opamp . You should refer to CMOS analog circuit design book (author: Allen, Holberg). They wrote in detail and step by step to design the 2 stage opamp. If you don't have much time, let focus on the chapter 5,6,7 in that book.
Good luck!
 

One possibility:
For the first stage, consider using a folded cascode topology (with PMOS inputs) to get high gain with good voltage headroom. For the second stage, use a topology for low output impedance and good swing - eg a common-source stage with active load.

You may want to consult a good analog IC design book (such as Razavi's) which will provide more detail.
 

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