Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Can not generate Verilog using FIFO Generator in IP catalog

Status
Not open for further replies.
S

slutarius

Full Member level 5
Joined
Oct 30, 2015
Messages
248
Helped
37
Reputation
74
Reaction score
36
Trophy points
28
Activity points
1,540
I opened a project and tried to make a general FIFO using "FIFO generator". Target language is set to Verilog. When it is done, but I received a VHDL type of source code instead of Verilog.
In same project, I took a Clock Wizard and can get Verilog type of an MCMM.

Does anyone meet the same issue ? Is that the exception for FIFO generator ?

I was trying to google it before hands, but no suitable info.
 

Some of the IP Xilinx produces only come in either VHDL or Verilog. I think it has more to do with which group (location) that implements the IP.
 
Thanks for your all comment. I will contact tool vendor.
It is available on Spartan6, but not on Kintex7 series though.
 

slutarius said:
Thanks for your all comment. I will contact tool vendor.
It is available on Spartan6, but not on Kintex7 series though.
Click to expand...

I predict the answer will be...

"Sorry, we don't have it in Verilog use the VHDL version Xilinx tools support mixed language designs"
 

ads-ee said:
I predict the answer will be...

"Sorry, we don't have it in Verilog use the VHDL version Xilinx tools support mixed language designs"
Click to expand...

I guess so. Moving up with a FIFO myself since it is not much on logic, but I expect something from STA and implementation. Thanks !
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top