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Round Robin Arbiter using Verilog HDL

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aravind9

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This is the Verilog HDL written for Round Robin Arbiter for two simple requests. When the req1 and req2 are high it should grant both requests in consecutive clock pulses, but this is not working when both requests are high. Please help me with this ASAP.

Code: 
module round_robin_arbiter(
    input clk,
    input rst,
    input req1,
    input req2,
    output reg gnt1,
    output reg gnt2
    );

reg temp;

always @(posedge clk or negedge rst)
begin
	if(!rst)
	begin
		gnt1 <= 1'b0;
		gnt2 <= 1'b0;
	end
		
	else if (req1)
	begin
	gnt1 <= 1'b1;
	gnt2 <= 1'b0;
	end
	
	else if(req2)
	begin
		gnt2 <= 1'b1;
		gnt1 <= 1'b0;		
	end
	
	else if (req1 && req2)
	begin
		gnt1 <= 1'b1;
		temp <= 1'b1;
		gnt2 <= temp;
	end
end

endmodule
 
Last edited by a moderator:

if..else chain is constituting a priority, if (req1 & req2) will be never true if you don't test it first.

The other question is if you get the intended signal timing, you didn't gave any specification about req1 and req2 behavior.
 

Code: 
else if (req1 && !req2)
...
else if (req2 && !req1)
allows the code to reach the condition (req1 && req2).

Your code still has issues as it's not a very good arbiter, it will have issues with gnt1 and gnt2 never going away until only one of the req1 is active or the arbiter is reset. The code is missing a lot of handshaking between the requests and grants and does not disallow multiple grants simultaneously.
 

Thanks for your response. I tried with what you have provided hint
else if(req1 && !req2)
......
else if (req2 && !req1)
......
else if (req1 && req2)
......

For this I'm getting output like gnt1 = 1 , gnt2 = 'X'

- - - Updated - - -

The condition is like to avoid the contention when req1 and req2 are high at the same time, which request gets the grant and if gnt1 is high first then gnt2 should be high in the next clock pulse.
 

you don't reset temp.

you should reset temp in every case except the (req1 && req2) case. in that case, temp <= ~temp, gnt1 <= ~temp, gnt2 <= temp.
 

I suggest you toss this code and just make a 3 state FSM with the following states:

no_req, gnt1, and gnt2.

no_req: does not have a grant to either 1 or 2 and no requests are active. goes to gnt1 if req1 is active, otherwise goes to gnt2 if req2 is active (priority encoded for req1)

gnt1: goes to no_req if req1 goes away and there is no req2, goes to gnt2 if there is a req2 (req1 is don't care, forces ping ponging between gnt1 and gnt2). spins in gnt1 as long as req1 stays active.

gnt2: goes to no_req if req2 goes away and there is no req1, goes to gnt1 if there is a req1 (req2 is don't care, forces ping ponging between gnt1 and gnt2). spins in gnt2 as long as req2 stays active.

I think that covers it, but you would have to verify that. If you make the FSM one-hot you can directly use the gnt1 and gnt2 states as the grant signals.
 

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