Logic family selection

I am designing a circuit, there I have a requirement, AND gate open input should be considered as logic low and when one of the input is logic low other input shouldn't be passed to output.
Open input will happen because of some failure. Otherwise always two inputs are connected to AND gate.

To treat open input as logic zero, I have selected PECL(Positive Emitter Coupled Logic).
In 2 input AND, if one of the transistor fails at short then other input will be passed to output.
So when one of the input is open and corresponding transistor is failed at short mode then other input is passing to output.

To avoid this,any other logic family can I use or is there any other solution.

It sounds as though you want the input to assume a default state when no signal is incoming. The normal method is to connect a resistor between the input and ground. (Typical value 5 k ohm.) It is a pull-down resistor.

An incoming signal overrides the default state.

If you want the default state to be high, then connect the resistor to supply +. (Then it is a pullup resistor.)

For low frequency requirements (1 MHz or less) it's hard to beat the old CD4000 CMOS family of logic circuits.
PECL is normally used only when you need the highest possible speed logic operation.

srikantamsravanthi said:

I am designing a circuit, there I have a requirement, AND gate open input should be considered as logic low and when one of the input is logic low other input shouldn't be passed to output.
Open input will happen because of some failure. Otherwise always two inputs are connected to AND gate.

To treat open input as logic zero, I have selected PECL(Positive Emitter Coupled Logic).
In 2 input AND, if one of the transistor fails at short then other input will be passed to output.
So when one of the input is open and corresponding transistor is failed at short mode then other input is passing to output.

To avoid this,any other logic family can I use or is there any other solution.

Click to expand...

Thank you for reply...
I have the requirement of
1. When open input comes output should go to zero. (Open will come with some failure,otherwise always 2 inputs will be connected)
2. The internal component, (eg. transistor or MOS) which takes input fails in short/open, output should goes to logic zero.
With pulldown resistor first requirement can be done.
How to achieve second.
Instead of using existed AND gate IC does is it possible to construct our own circuit with these requirements.

The way to do that is (...laborious unless you use a program that quickly calculates it all for you) to make a truth table and fill it in to see what inputs create the output you need. That usually goes with Karnaugh Mapping. And from either table you can deduce the logic device, or combination you need.
I think you want to make a combinational logic gate, which means combining AND/XOR/etc. to get the result you want, but there may be a far better KISS solution I can't think of.

...I made a gate that had 2 inputs (a few days headache), one high input turned off the device, the other high input didn't - that was what I needed, not great but functional, if you want to adapt that to function #2 I can send you a schematic that you could invert and no doubt greatly improve, or use as a base to think of a better combination.

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Hi, this is what I meant, it's pretty rubbish but works - needed a gain stage at the output in my case as I made it with logic level MOSFETS (bad idea), but you could perhaps invert the function by using other types of gate and/or adapt it and improve the basic idea a lot