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corrupted data read from DDR3, refresh time limitation? Limitation of DDR3 technology

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picnanard

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Hi,
I am new in DDR3 developments.
I am trying a brute force read/write DDR3 sequence. The test pattern is a 32 bits counter big endian. At first I write a one shot 128 Mbytes packet in then DDR3 and then I read them. This represents approximately one second of data storing. I remark that the 2 first Mbytes of data stored in DDR3 are OK but the all the rest is corrupted. Indeed, as you can see in the Figure below, the highest byte “00” of the 32-bit counter become a “08”.
Bytes that are stored for a “long time”, as the highest byte of my counter, seems to be lost after an unknown time. Is this due to a problem of refresh cycle?



read.png



The Chipscope DDR3 data acquisition show this problem may come from DDR3 controller or DDR3 memory.

chipscope.PNG

Is there any limit time duration of data storing in DDR3? Do I reached the refresh cycle time limitation (if any?)? Do I forgot any important parameter?

The Chipscope DDR3 data acquisition when i write in DDR3 memory.(addr f8008)

chipscope_write.png
chipscope_write.png


Thanks,



Test configuration :

ISE 14.7 with MIG7 1.9

MT41K256M16xx – 125, 256 Mbyte – 16 bits.
 

Hi,

I can try it but ddr3 controller always work 100MHz, it's lower speed for a ddr memory.
 

you can write once and then cycle the read test. This will show if your theory is correct. Likewise, you can check to make sure you never write that to device.

It it the same bit that fails every time. However a 16b device with a burst should be holding that line low. This is also odd because 128MB @ 32bit means that bit shouldn't even be set within the FPGA logic, so a 1 should never be written on that line.

The only other thing I can think of now is if you have the DCI settings on the device correct. If you don't have the calibration resistors, or if the power to the back is not correct during/after FPGA power on, the output impedance might cause some issues. I wouldn't expect it to cause this exact issue, but I could accept it.
 

Hi,

Are you testing on a real device?

Is there the possibility that an address line or data line is corrupted by short/open/ connection to another line?

Klaus
 

Hello,

Yes vGoodtimes i trying just one write packet for to be sure. The DCI is enabled.


But this problem is very strange. Because in the same fpga design I can test several test pattern and the pattern below work, I write-read 128 Mbyte twelve times and this pattern work any error.
premier_motif.PNG
But with test pattern below counter little endian same problem big endian! All my design is coded with 128 bits data width. Currently the problem come on the same byte in 32 bit counter.
little_endian.PNG


Thank you for you help.

- - - Updated - - -

Thank you very much vGoodtimes and all thank you
"you can write once and then cycle the read test"
i find problem on fsm transfert data from ddr3 to fifo pipe out usb3.

Now i transfert 17Go on usb3 via ddr3 DMA the data are correct.
 

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