kidi3
Full Member level 1
I am having some issues it seems with the input i've received.. It doesn't seem to be arranged it correct way as it supposed..
I tested with this piece of code
But it seems to keep showing value of others.. Instead what i provide it with.
Am i storing the bit incorrectly ?
- - - Updated - - -
For instance
V_ref = V_dd = CH0 = 3.3 V from FPGA
But the output DOUT = 0111111011.. or something like that.. it never bed 1111111111...
I tested with this piece of code
Code:
if RX = "0111111111" then
tx_pwm <= "11";
elsif RX = "000000000" then
tx_pwm <= "00";
else
tx_pwm <= "10";
end if;
But it seems to keep showing value of others.. Instead what i provide it with.
Am i storing the bit incorrectly ?
Code:SPI_state: process(newClock) begin if falling_edge(newClock) then case state is when start => debug_TX <= "00000001"; CS <= '1'; MOSI <= '0'; RX <= "0000000000"; state <= state2; when state2 => -- Send init bits. CS <= '0'; shift_counter <= shift_counter - 1; TX <= TX(N-1 downto 0) & TX(N); MOSI <= TX(N); if shift_counter = 0 then MOSI <= '0'; shift_counter<= 10; state <= state3; end if; when state3 => MOSI <= '0'; CS <= '0'; -- Last bit init bit; state <= state4; when state4=> CS <= '0'; --T_sample from falling - falling state <= state6; when state6=> CS <= '0'; -- Read shift_counter <= shift_counter - 1; RX <= RX(8 downto 0) & MISO; if shift_counter = 0 then MOSI <= '0'; shift_counter<= N; state <= start; end if; when others => state <= start; end case; end if; end process;
- - - Updated - - -
For instance
V_ref = V_dd = CH0 = 3.3 V from FPGA
But the output DOUT = 0111111011.. or something like that.. it never bed 1111111111...