Pattern Matching Counter in Verilog

Plz tell how to do parts a, b, c.

Design algorithmic state machine comprising of controller and data path implemented in RTL based model, which can
find how many times a 4-bit feedable virus pattern occurs in a data file (data file is attached).

a) Draw structural block diagram of controller and data path along with signals.
b) Draw ASMD chart of the state machine.
c) Give RTL level Verilog description of controller (FSM) and data path.


Example for pattern matching: In pattern matching, a sequence is scanned bit by bit and once a required pattern is
found, the scan restarts from the next bit. For example, we have 11011101011 in the data file and pattern to be fed is
1011, the scanning process start form the left, we have 11 at that start (first and second bit) that is different from the
virus pattern (1011), since it’s a mismatch, the scan starts form the second bit. Upon restarting the scan from second
bit, we have found that the virus pattern exists in the next four bits, so the counter is incremented to one and the scan
restarts form sixth bit and this process continues until the end of file.

Input phase: Data files that contains large strings of binary sequence; is downloaded, either in the flash or in FPGA
memory. Use slide switches (SW0, SW1, SW2 and SW3) for feeding a 4 bit binary pattern.

Output phase: A Reset button (pushbutton BTN0) that resets the value of counter, and a Go button (pushbutton BTN1)
that displays the counter value (number of times the virus pattern exists in a data file) on both seven segment displays
(in decimal form) and on 8 LEDs (in binary form). Considering the above example, the seven segment should display 1
as well as the LED should display the binary form of 1.

arfaengg said:

Plz tell how to do parts a, b, c.
a) Draw structural block diagram of controller and data path along with signals.
b) Draw ASMD chart of the state machine.
c) Give RTL level Verilog description of controller (FSM) and data path.

Click to expand...

You do know homework is given so you learn how to do these things yourself, having forum members on edaboard do them for you won't give you the expertise to do them yourself when you graduate from school.

a) get a piece of paper and start drawing boxes and label them with things like FF, ADDER, MUX, etc.. Then connect them with lines labeled like, select, address, data, enable, clock etc. e.g. like these images.
This is where you design the controller and datapath.

b) Shows bubble diagrams and the corresponding ASM http://dejazzer.com/ee478/lecture_notes/lec11_fsmd.pdf

c) Power up your computer, after doing a & b, then translate the design into a Verilog hardware description using your favorite text editor. Of course that will require that you learn Verilog first (it's amazing that the first 3 tutorials, from universities no less, returned by google all use antiquated pre-2001 port declarations...hello it's 2015 14 years after the standard was introduced!).