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STA aspect: What will be the impact design if we make to much tight transition time.

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mepriyasingh

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STA aspect: What will be impact on design if we make to much tight transition time.

As per STA aspect: What will be the impact on design if we make to much tight transition time. what prime time will do..
 
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morris_mano said:
If you have tight transition time during synthesis, may be fanout will be reduced.
Click to expand...


Thanks
Can you elaborate this so that i am able to understand better.
Can any body else please.

Thanks in Advance
 

mepriyasingh said:
Thanks
Can you elaborate this so that i am able to understand better.
Can any body else please.

Thanks in Advance
Click to expand...
fanout = number of loads on a net.

therefore...
more loads = slower signal transitions
less loads = faster signal transitions
 
Re: STA aspect: What will be impact on design if we make to much tight transition tim

mepriyasingh said:
As per STA aspect: What will be the impact on design if we make to much tight transition time. what prime time will do..
Click to expand...

If you over constrain max_transition for signals,

1. Buffer counts will increase to meet the constraint
2. Cells will be faster but delay due to buffers will add up much higher
3. Congestion due to increased buffer counts
4. OCV impact will be high if you increase in the number of buffers in clock tree. Increase in #buffers in clock tree --> more OCV --> higher skew. [ OCV: On Chip Variation ]
 
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