Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Use generic in package: VHDL

Status
Not open for further replies.
J

jeetesh

Newbie level 4
Joined
Dec 19, 2013
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
54
I have defined a generic in entity and I want to pass it to package. How to do this, without using component and others. I read somewhere that VHDL-2008 provides this feature. But I don't know how to use it? This is what I am trying to do (just an example):

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

library ieee;
use ieee.std_logic_1164.all;
 
package pack is
   generic(N: integer := 15);
   port ( in1, in2: std_logic_vector(N downto 0));
   function and15(in1, in2: std_logic_vector) return std_logic_vector;
end pack;
 
package body is
    function and15(in1, in2: std_logic_vector) return std_logic_vector is
    variable result: std_logic_vector(N downto 0);
    begin
         result := in1 and in2;
    end pack;
 
library ieee;
use ieee.std_logic_all;
use work.pack.all;
 
entity andgate is
   generic(N: integer := 15);
   port (in1, in2: std_logic_vector(N downto 0);
              out1: std_logic_vector(N downto 0));
end andgate;
 
architecture arch of andgate is
begin
      out1 <= and15(in1, in2);
end arch;
 
Last edited by a moderator:

You are making simply things complicated. No VHDL2008 needed, just write
Code: 
package pack is
function and15(in1, in2: std_logic_vector) return std_logic_vector;
end pack;

package body pack is
  function and15(in1, in2: std_logic_vector) return std_logic_vector is
  variable result: std_logic_vector(in1'left downto 0);
  begin
    result := in1 and in2;
  return result;
-- or simply return in1 and in2;
end pack;
 
FvM said:
You are making simply things complicated. No VHDL2008 needed, just write
Code: 
package pack is
function and15(in1, in2: std_logic_vector) return std_logic_vector;
end pack;

package body pack is
  function and15(in1, in2: std_logic_vector) return std_logic_vector is
  variable result: std_logic_vector(in1'left downto 0);
  begin
    result := in1 and in2;
  return result;
-- or simply return in1 and in2;
end pack;
Click to expand...

Thank you FvM for your reply. We can design this like you did, but can we pass generic value to a package. If yes, then how? Considering this example.
 

As said, generic isn't needed in the present case. A function parameter connected to a constant should work in the general case. At least it did for me up to now.
 

When you write a package with a generic - you cannot use the package directly until you have created an instance of it.

Code VHDL - [expand]
1
2
3
4
5
6
7
8

package pack_inst is new work.pack
    generic map( 
        N => 100
    );
 
--and then in code:
 
use work.pack_inst.all;


I assume you're only going to use this in simulation - no synthesis tools (at least Quartus, ISE and Vivado) support generics on packages (even though they claim vhdl 2008 support).

- - - Updated - - -

But I agree with FvM - in your example a generic is not needed - dont overcomplicate code.
 
Thank you FvM and TrickyDicky. I know generic is not needed in my example, but I want to use this in some other designs. That was just an example, not design.

TrickyDicky, I got it. Thanks for suggesting the instance of the package. I am using synplify and will check wether its gonna work there or not..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top