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Verilog or SystemVerilog signal initialization rule, Mentor: Multiply Driven

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legendbb

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I used to initialize all my signals in VHDL.

Attempted same thing in Verilog or SystemVerilog.

Code: 
logic dut_output_sig = 1'b0;
dut:(.output(dut_output_sig))

But above initialization doesn't seem to work when the signal is used to connect to my dut:eek:utput

Mentor Error: vsim-3839: Variable *, driven via a port connection, is multiply driven.

Dropping the initialization made it work. Which tells me Verilog/SV doesn't have the same init rule as VHDL?

Not sure if there are other GOTCHAs, or if I am taking this right.

Want to listen to experts,

Thanks,:roll:
 

That is correct. A variable is only allowed to have exclusively: one continuous assignment, or any number of procedural assignments. An output is considered a continuous assignment to the the variable in the port connection, and a variable initialization is considered a procedural assignment before time 0. You can't have both.

I'm not sure what you are trying to achieve with the variable initialization. Even if it were allowed, it would immediately be overwritten with the value driven by the output.
 
dave_59 said:
That is correct. A variable is only allowed to have exclusively: one continuous assignment, or any number of procedural assignments. An output is considered a continuous assignment to the the variable in the port connection, and a variable initialization is considered a procedural assignment before time 0. You can't have both.

I'm not sure what you are trying to achieve with the variable initialization. Even if it were allowed, it would immediately be overwritten with the value driven by the output.
Click to expand...

Thanks Dave, I was thinking about posting into Verification Academy and expected your attention. Magically you showed up here too.

Thanks a lot, I just played with SV in ModelSim no particular reason for the initialization.

Thanks again for sharing your knowledge. :thumbsup:
 

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