current flow through diff pair doesn't match theory

Hello,
Please refer to the images attached.
I'm hoping someone can shed some light on this because I'm really confused about this. I have a simple diff pair where I sweep, one input (ip) and hold the other (in) at vdd/2. At ip = 0V, I would expect the entire bias current to flow through the device connected to "ip" and when ip is at VDD, I would expect the entire current to flow through the device connected to "in". The red waveform is the current through "ip" and the green is the current through "in" device. The yellow trace is just the sweep voltage on "ip".
The y-axis on the left is current and the one on the right is voltage.
When ip=0V, the waveforms make sense but not when "ip" approaches vdd. The current levels don't get near where they should be. If I remove the nmos devices, the waveforms match the theory. I've swept both width and length of the nmos devices to no avail.

Can anyone explain to me what might be going on? Am I missing something here?

Thanks

Plot M1 and M2 Vds and you'll understand why this happens.

Hi FvM,
I did as you suggested. Let me see if I'm interpreting this righ: drain-source voltage of M2 get shorted while drain source voltage of M1 becomes high impedance which is counter-intuitive and seems to contradict the following analysis. I would expect M2 to be highZ when ip is high --> drain of M3 to go to ground and so drain of M1 to to go to vdd. Is this the circuits attempt to satisfy kirchhoff's current law. The current is supposed to flow through M1 but the lateral electric field (VDS) of M1 is going towards zero. So although M2 is supposed to be opened, it overcompensates and shorts its drain and source to allow some current to flow through it which then open makes M4 conduct.

The plot is attached.
the vds plots are circled in blue. yellow is vds of M1 and pinkish is vds of M2.
Thanks for the quick response.

Your schematics and graphs are "backwards" and because they are extremely dim negatives then I must wait for darkness to see anything. Why didn't you make them positives (black lines on a white background) like almost all other schematics?

Yeah, I just took a quick snapshot from cadence but will do next time.

Let me see if I'm interpreting this righ: drain-source voltage of M2 get shorted while drain source voltage of M1 becomes high impedance which is counter-intuitive and seems to contradict the following analysis.

Click to expand...

I think you confused M1 and M2 in the annotation of the latest plots. What happens is that M2 is terminated with the current mirror input, so it's always in saturated operation while M1 Vds is collapsing as soon it's drain current exceeds the current mirror output current.

You need a low impedance termination of M1/M4 drain node to allow full M1 current.