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    Minimum required constraints while synthesis?

    What are the minimum required constraints to be given while synthesising a design?
    1. clock period
    2. input delay
    3. output delay
    4. clock uncertainity
    5. clock latency
    6. set load
    Other than the constraints listed above, what are the basic constraints required?

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    Re: Minimum required constraints while synthesis?

    Depends on a lot of factors. Whether you are synthesizing a design for an ASIC or FPGA, what are your requirements.

    I had synth. a microprocessor design to be implemented on a FPGA using only the create_clock constrain, nothing else.
    FPGA enthusiast!



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    Re: Minimum required constraints while synthesis?

    I am trying to study ASIC synthesis by myself. I took a System on Chip using OR1K processor. I am not given any constraints and I am trying to get familiarize with the different synthesis constraints. So, what all could be the typical constraints?



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    Re: Minimum required constraints while synthesis?

    In that case I guess you have answered your own question in the 1st post! :)
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    Re: Minimum required constraints while synthesis?

    I would suggest to have the following constraint first.

    1. clock period
    2. input delay
    3. output delay
    4. clock uncertainity
    5. clock latency
    6. set load
    7. set input transition
    8. False Path / Multi-Cycle Path ( between the clock domains if any ).



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