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SDC is correct or not during synthesis

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sun_ray

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How to check the SDC is correct or not at RTL syntheis level?
 

Check with the designer about the constraints...That should do...
 

Is there any command of DC that will help to undderstand SDC may have problem and once we know there is problem we approach to the designer?
 

You can try to use command check_timing ...
It will issue some warnings/errors: like unconstrained input ports (no set_input_delay) etc
 

You can try to use command check_timing ...
It will issue some warnings/errors: like unconstrained input ports (no set_input_delay) etc

What else will check_timing dump? What options are needed to be used with check_timing? Should check_timing be used before compile_ulta or after compile_ultra?

Regards
 

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