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    SDC is correct or not during synthesis

    How to check the SDC is correct or not at RTL syntheis level?

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    Re: SDC is correct or not during synthesis

    Check with the designer about the constraints...That should do...



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    Re: SDC is correct or not during synthesis

    Is there any command of DC that will help to undderstand SDC may have problem and once we know there is problem we approach to the designer?



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    Re: SDC is correct or not during synthesis

    I am not aware of any...



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    Re: SDC is correct or not during synthesis

    You can try to use command check_timing ...
    It will issue some warnings/errors: like unconstrained input ports (no set_input_delay) etc



  6. #6
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    Re: SDC is correct or not during synthesis

    Quote Originally Posted by oratie View Post
    You can try to use command check_timing ...
    It will issue some warnings/errors: like unconstrained input ports (no set_input_delay) etc
    What else will check_timing dump? What options are needed to be used with check_timing? Should check_timing be used before compile_ulta or after compile_ultra?

    Regards



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  7. #7
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    Re: SDC is correct or not during synthesis

    man check_timing



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