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[Moved] analog layout ( capacitor).

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kvidhya

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In 110nm tech while running drc
for capacitor i am getting this error
how can i rectify this



"in n_well , poly 1 overlap n+ diffusion is not allow".
 

Isn't the DRC error message clear enough?
 

Hi,

Don not try to create nmos in nwell by puuting poly cap(you might be using..i feel),put outside nwell...correct me if i am wrong...
 

thank u every one for responce
the cells which i got from foundry error pron in that cells
 

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