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[moved] Vcd dump issues of simple verilog code

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mustafa_110

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Hi All,

I am new to the frontend. My expertise lies mostly in the back end . I am trying my hand at verilog coding and simulations using ncvim. Some how I a not able to dump a proper vcd file to view in simvision. Can someone please help me to figure out the issue.

This is the content of a simple mux ( file my_mux.v)

Code Verilog - [expand]
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`timescale 1ns/10ps
module my_mux (a , b  , s , z) ;
input a , b , s ;
output z ; 
 
assign z = (s) ? a : b ;
endmodule
 
This is the content of the testbench code as mentioned below. ( file my_mux_tb.v )
 
`timescale 1ns/10ps
module testmux;
reg a, b, s ;
 
wire out ;
 
my_mux inst (a , b  , s , out) ;
 
initial 
 
begin 
    $dumpfile("testmux.vcd");
    $dumpvars();
    a = 0 ;
    b = 1 ; 
    s = 0 ;
    #1;
 
    a = 1 ;
    #1;
 
    s = 1 ;
    b = 0 ;
 
    #1;
    $finish;
 
end
endmodule


These are the commands use to compile , elab and simulate and then view the waveform.

Code: 
ncvlog my_mux.v my_mux_tb.v -messages
ncelab testmux -messages
ncsim testmux

However the vcd file does not contact the information required to view the waveform in simvision. As a result there are no waveforms to view.
The content of the vcd file is as mentioned below.

Code: 
$date
    Jun 27, 2015  23:09:45
$end
$version
    TOOL:	ncsim	14.20-s002
$end
$timescale
    10 ps
$end
$enddefinitions $end
$dumpvars
$end
#300

Can someone please help me get some waveform so that I can view the same in simvision.

Regards,
Mustafa
 
Last edited by a moderator:

Pass option "access -r" to ncelab.
Check warnings from ncsim without this option:
*W,DVEXACC2: someobjects excluded from $dumpvars due to -access -R.
 

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