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  1. #1
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    [BackEnd] Multi Power Domain Design (using UPF)

    Hi All,

    Do someone can tell more about the Multi Power Domain Design (using UPF)?

    As far as I know, UPF is a TKL file, which define the power optimizations during synthesis. Correct?

    But how can it do it?

    Thank you!

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  2. #2
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    Re: [BackEnd] Multi Power Domain Design (using UPF)

    well it is more to do with IP generation ....the IP provider provides UPF file for the blocks (voltage of operation,shutdown,powerdown,isolation cells etc)....basically anything which cannot be provided in Verilog and .libs. you should have UPF file for the .libs or .libs should be generated with UPF parameters like power_down_function, isolation cells)....

    then there are other UPF constraints that are needed at the block level : if block A is working at 1V and block B is working at 0.75v then UPF constraints have to be written at the interface level. IEEE_standard 1801-2013 which covers how UPF can be used at various of design cycle and it is not just synthesis.


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