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help!!!! something doesnt work!!!!

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jony

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i wrote this code that describe a signal mapping block of pi/4 dqpsk.
but the rom address doesn't increase.
can somebody help me?

this is the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all ;

entity signal_mapping1 is
port( Clock : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
in_I : in std_logic;
in_Q : in std_logic;

out_I: out REAL ;
out_Q: out REAL
);
end signal_mapping1;

--------------------------------------------------------------

architecture Behav of signal_mapping1 is


type ROM_Array is array (0 to 15)
of real;

constant Content: ROM_Array := (
0 => 1.0, -- Suppose ROM has
1 => 0.0, -- prestored value
2 => 0.70710_67811_86547_52440, -- like this table
3 => 0.70710_67811_86547_52440, --
4 => 0.0, --
5 => 1.0, --
6 => -0.70710_67811_86547_52440, --
7 => 0.70710_67811_86547_52440, --
8 => -1.0, --
9 => 0.0, --
10 => -0.70710_67811_86547_52440, -- 11 => -0.70710_67811_86547_52440,
12 => 0.0, --
13 => -1.0, --
14 => 0.70710_67811_86547_52440,
15=> -0.70710_67811_86547_52440,
OTHERS => 505.0 --
);
-- define the states of FSM model

signal address_i:integer := 0;
signal address_q:integer := 1;
begin
process(Clock, Reset,in_q,in_i )

begin

if( Reset = '1' ) then
out_i <= Content(0);
out_q <= Content(1);

elsif( Clock'event and Clock = '1' ) then
if Enable = '1' then

if(in_q='0' and in_i='0' ) then
out_q <= Content(address_q+2);
out_i <= Content(address_i + 2);
address_i <= address_i+2;
address_q <= address_q+2;



elsif(in_q='1' and in_i='0' ) then
out_q <= Content(address_q+4);
out_i <= Content(address_i + 4);
address_i <= address_i+4;
address_q <= address_q+4;


elsif(in_q='0' and in_i='1' ) then
out_q <= Content(address_q+6);
out_i <= Content(address_i + 6);
address_i <= address_i+6;
address_q <= address_q+6;


elsif(in_q='1' and in_i='0' ) then
out_q <= Content(address_q+8);
out_i <= Content(address_i + 8);
address_i <= address_i+8;
address_q <= address_q+8;
end if;
else
out_q <= 505.0;
out_i <= 505.0;
end if;

end if;
end process;
end Behav;

--------------------------------------------------------------
 

I think you have two statements of elsif that the inputs in_q and in_i have the same value (in_q = '1', in_i = '0') :

Code: 
 elsif(in_q='1' and in_i='0' ) then
out_q <= Content(address_q+4);
out_i <= Content(address_i + 4);
address_i <= address_i+4;
address_q <= address_q+4; 

 elsif(in_q='1' and in_i='0' ) then
out_q <= Content(address_q+Cool;
out_i <= Content(address_i + Cool;
address_i <= address_i+8;
address_q <= address_q+8;

Probably you wanted one of them to be in_q = '1' and in_i = '1'. Otherwise you have race condition.

If you allow me I would like to note you that when you have a clocked process in the sensitivity list you declare the clock and the reset. You don't need the other inputs because they are checked at every rising or falling edge of the clock. So the sensitivity list is:

Code: 
 process(Clock, Reset)
 

you were right but still it doesn't work
here is the correct code and the test bench
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;		 
use ieee.std_logic_unsigned.all;
use ieee.math_real.all ;

entity signal_mapping1 is
port(	Clock   : in std_logic;
	Reset	: in std_logic;	
	Enable	: in std_logic;
	in_I	: in std_logic;
	in_Q	: in std_logic;

    out_I:  out REAL ;
    out_Q: out REAL
);
end signal_mapping1;

--------------------------------------------------------------

architecture Behav of signal_mapping1 is 


    type ROM_Array is array (0 to 15) 
	of real;

    constant Content: ROM_Array := (
        0 => 1.0,		-- Suppose ROM has 
        1 => 0.0,		-- prestored value
        2 => 0.70710_67811_86547_52440,		-- like this table
        3 => 0.70710_67811_86547_52440,       		--
        4 => 0.0,		--
        5 => 1.0,       		--
        6 => -0.70710_67811_86547_52440,		--
        7 => 0.70710_67811_86547_52440,      		--
        8 => -1.0,       		--
        9 => 0.0,       		--
        10 => -0.70710_67811_86547_52440,		--
    	11 => -0.70710_67811_86547_52440,       	--
        12 => 0.0,      		--
        13 => -1.0,		--
        14 => 0.70710_67811_86547_52440,
	    15=> -0.70710_67811_86547_52440,
	OTHERS => 505.0		--
	); 
	
   
 signal	address_i:integer := 0;
 signal	address_q:integer := 1;
begin
    process(Clock, Reset)
    begin
        if( Reset = '1' ) then
	     out_i <= Content(0);
		out_q <= Content(1);
        elsif( Clock'event and Clock = '1' ) then
	    if Enable = '1' then 
			
		if(in_q='0' and in_i='0' ) then
		    out_q <= Content(address_q+2);
			out_i <= Content(address_i + 2);
			address_i <= address_i+2; 
			address_q <= address_q+2; 
			
			
			
		elsif(in_q='1' and in_i='0' ) then
		    out_q <= Content(address_q+4);
			out_i <= Content(address_i + 4);
			address_i <= address_i+4; 
			address_q <= address_q+4; 
				
		
		elsif(in_q='0' and in_i='1' ) then
		    out_q <= Content(address_q+6);
			out_i <= Content(address_i + 6);
			address_i <= address_i+6; 
			address_q <= address_q+6; 
			 
			
		elsif(in_q='1' and in_i='1' ) then
		    out_q <= Content(address_q+8);
			out_i <= Content(address_i + 8);
            address_i <= address_i+8; 
			address_q <= address_q+8; 
			 	end if;
            	else
                    out_q <= 505.0;
					out_i <= 505.0;
            	end if;
	  
        end if;
    end process;
end Behav;

--------------------------------------------------------------tb-------------------

	 library ieee ;
 use ieee.std_logic_1164.all;  
 entity	signal_mapping_tb is
 end signal_mapping_tb ;
 architecture  signal_mapping_tb_arc of signal_mapping_tb  is

component signal_mapping1 is
	port(	Clock   : in std_logic;
	Reset	: in std_logic;	
	Enable	: in std_logic;
	in_I	: in std_logic;
	in_Q	: in std_logic;
    out_I:  out REAL ;
    out_Q: out REAL
);
		 
			
end component;
	signal enable_tb   : std_logic;
    signal	 clock_tb : std_logic :='1';
	signal reset_tb   : std_logic;
	signal in_i_tb :  std_logic;
	signal in_q_tb :  std_logic;
	signal out_i_tb :real;
	signal out_q_tb:real ;
	
	constant  clk_time: time := 50 ns;  
	begin
								 
UUT : signal_mapping1
port map (
			enable => enable_tb,
			CLOCK => clock_tb,
		    reset => reset_tb,
	    	in_i => in_i_tb,
		  	in_q => in_q_tb	,
		 	out_i => out_i_tb,
		    out_q => out_q_tb
		);	 
	clock_proc: process	 
	begin
	  clock_tb <= not(clock_tb) ;
	   wait for clk_time;
	end process 	clock_proc;	  
reset_in:PROCESS
		BEGIN
	   reset_tb<= '1';
	    WAIT FOR 10 ns;
	    reset_tb <= '0';
	    WAIT;
	END PROCESS reset_in;
	enable_in:PROCESS
		BEGIN
	   enable_tb<= '1';
	    WAIT FOR 10 ns;
	    enable_tb <= '0';
	    WAIT;
	END PROCESS enable_in;

				in_q_tb	<= '0','1' after 200 ns,'0' after 400 ns,'1' after 600 ns
	,'1' after 800 ns,'0' after 1000 ns,'1' after 1200 ns,'0' after 1400 ns,'1' after 1600 ns
	,'1' after 1800 ns,'0' after 2000 ns;
	in_i_tb	<= '0','1' after 200 ns,'0' after 400 ns,'1' after 600 ns
	,'0' after 800 ns,'1' after 1000 ns,'1' after 1200 ns,'0' after 1400 ns,'1' after 1600 ns
	,'0' after 1800 ns,'1' after 2000 ns; 

	end signal_mapping_tb_arc;
 

Code: 
 enable_in:PROCESS
      BEGIN
      enable_tb<= '1';
       WAIT FOR 10 ns;
       enable_tb <= '0';
       WAIT;
   END PROCESS enable_in;

I think in your testbench you keep the enable signal high for a very short time. From what I saw from your code, the address is incremented when Enable is high. I believe you wanted to write sth like that:

Code: 
 enable_in:PROCESS
      BEGIN
      enable_tb<= '0';
       WAIT FOR 10 ns;
       enable_tb <= '1';
       WAIT;
   END PROCESS enable_in;
 

thanks u but now i have a new problem.
how can i make the rom address increase in circular mode?
address4+14=address 2
 

For circular mode, your code should be modified like this:

Code: 
if(in_q='0' and in_i='0' ) then
   if (address_i = 14 and address_q = 15) then
         address_i <= 0;
         address_q <= 1;  
         out_q <= Content(address_q);
         out_i <= Content(address_i);
         
   else
          out_q <= Content(address_q+2);
         out_i <= Content(address_i + 2);
         address_i <= address_i+2;
         address_q <= address_q+2; 
   end if;

   elsif(in_q='1' and in_i='0' ) then
      
      if (address_i >= 12 and address_q >= 13) then

       out_q <= Content(address_q - 12);
         out_i <= Content(address_i - 12); 
        address_i <= address_i - 12;
         address_q <= address_q - 12;      
                 
     else  
          out_q <= Content(address_q+4);
         out_i <= Content(address_i + 4);
         address_i <= address_i+4;
         address_q <= address_q+4; 
    end if;

    elsif(in_q='0' and in_i='1' ) then
  
       if (address_i >= 10 and address_q >= 11) then

         out_q <= Content(address_q - 10);
         out_i <= Content(address_i - 10);
         address_i <= address_i - 10;
         address_q <= address_q - 10; 
      else
          out_q <= Content(address_q+6);
         out_i <= Content(address_i + 6);
         address_i <= address_i+6;
         address_q <= address_q+6; 
    end if;

   elsif(in_q='1' and in_i='1' ) then
         
     if (address_i >= 8 and address_q >= 9) then
     
       out_q <= Content(address_q - 8);
         out_i <= Content(address_i - 8);
            address_i <= address_i - 8;
         address_q <= address_q - 8; 

     else

      out_q <= Content(address_q+8);
         out_i <= Content(address_i + 8);
            address_i <= address_i+8;
         address_q <= address_q+8; 
     end if;

I hope this will help you.
 

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