+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Full Member level 4
    Points: 1,741, Level: 9

    Join Date
    Jul 2014
    Posts
    216
    Helped
    14 / 14
    Points
    1,741
    Level
    9

    Verilog Selective Synthesis, Advise on Code Structure

    hi,

    i had designed three modules(using verilog) and make it together using a wraper.
    example

    module top()

    ::::::::::::
    :::::::::::

    A uut();

    B uut();

    c uut();

    endmodule

    after this, when i synthesis the top module , i need only MODULE A to get synthesized and not B and C. then next time only B not A and C
    is there any way to do this.

    thanks & regards
    Last edited by dipin; 15th June 2015 at 10:56.

    •   AltAdvertisment

        
       

  2. #2
    Advanced Member level 2
    Points: 3,454, Level: 13

    Join Date
    Apr 2011
    Location
    India
    Posts
    552
    Helped
    126 / 126
    Points
    3,454
    Level
    13

    re: Verilog Selective Synthesis, Advise on Code Structure

    U can use an `ifdef while instantiating the modules.


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  3. #3
    Full Member level 4
    Points: 1,741, Level: 9

    Join Date
    Jul 2014
    Posts
    216
    Helped
    14 / 14
    Points
    1,741
    Level
    9

    Re: Verilog Selective Synthesis, Advise on Code Structure

    HI,
    `define B
    module top()

    ::::::::::::
    :::::::::::
    `ifdef A
    A uut();
    `elsif B
    B uut();
    `elsif C
    C uut();
    `endif
    endmodule

    hi i have selected like this and now its working. but got a problem. i am not able to synthesis it?
    anybody know how to solve this
    thanks in advance
    Last edited by dipin; 16th June 2015 at 07:53.



    •   AltAdvertisment

        
       

  4. #4
    Advanced Member level 2
    Points: 3,454, Level: 13

    Join Date
    Apr 2011
    Location
    India
    Posts
    552
    Helped
    126 / 126
    Points
    3,454
    Level
    13

    Re: Verilog Selective Synthesis, Advise on Code Structure

    By any chance are you keeping the define name same as the module name? Please post the error?


    1 members found this post helpful.

  5. #5
    Full Member level 4
    Points: 1,741, Level: 9

    Join Date
    Jul 2014
    Posts
    216
    Helped
    14 / 14
    Points
    1,741
    Level
    9

    Re: Verilog Selective Synthesis, Advise on Code Structure

    hi,
    thanks sarath, its solved.



--[[ ]]--