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[SOLVED] Verilog Selective Synthesis, Advise on Code Structure

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dipin

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hi,

i had designed three modules(using verilog) and make it together using a wraper.
example

module top()

::::::::::::
:::::::::::

A uut();

B uut();

c uut();

endmodule

after this, when i synthesis the top module , i need only MODULE A to get synthesized and not B and C. then next time only B not A and C
is there any way to do this.

thanks & regards
 
Last edited:

U can use an `ifdef while instantiating the modules.
 
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    dipin

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HI,
`define B
module top()

::::::::::::
:::::::::::
`ifdef A
A uut();
`elsif B
B uut();
`elsif C
C uut();
`endif
endmodule

hi i have selected like this and now its working. but got a problem. i am not able to synthesis it?
anybody know how to solve this
thanks in advance
 
Last edited:

By any chance are you keeping the define name same as the module name? Please post the error?
 
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    dipin

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hi,
thanks sarath, its solved.
 

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