Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
1. report_qor (synopsys DC) - to see overall statistics of setup WNS/TNS.
2. report_timing - to see setup slack of the defined path.
3. report_power - if power is the important goal.
4. if you did physical synthesis (DC topo) - see congestion report, maybe you will need to change floorplan.
DC applying some default activity (do not remember exdact numbers). It will give rough estimation. Still, you can apply your own activity during synthesis, in order to do proper power optimisation during synthesis and obtain real power numbers. Your activity may be estimation activity (for example, equal for all nets) or the real numbers obtained from RTL simulation.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
