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  1. #1
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    Large Transistor Layout Design Using Cadence

    I have transistor of 40/0.18 micro meter size, I am doing layout design in the cadence tool, I am cutting down the size into 8 fingers, I am not very sure about the width and length of the substrate.?

    I have read few comments regarding ring structure of the substrate.
    I would like to know in detail about this problem.? if somebody can help I will be very thankful.

    Also I am doing layout of 100pF capacitor, i am using mimcap which is already available in gpdk180 libraries. The size for this large cap is covering almost full area in the design. If sombody can provide the document containing layout design of the capacitor it will help me.

    Thanks
    Mahesh

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  2. #2
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    Dominik Przyborowski's Avatar
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    re: Large Transistor Layout Design Using Cadence

    Check the design rules - the maximum distance between substrate/well contacts is defined on around 20-40 um, so your 8 fingers 40/0.18 fet will take around 8 x 4 um^2 so If You only make a substrate contacts around him everything will be ok. BTW. It is not a large transistor. Large transistors has for example a mm width

    Which circuit needs 100pF capacitor? If it possible use moscap instead of mimcap.



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  3. #3
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    Re: Large Transistor Layout Design Using Cadence

    Quote Originally Posted by Dominik Przyborowski View Post
    ... so your 8 fingers 40/0.18 fet will take around 8 x 4 um^2 ...
    8 x 5 (µm)2 of course. Better take a calculator, Dominik! SCNR. No harm meant!



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  4. #4
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    Re: Large Transistor Layout Design Using Cadence

    It meant to be 5×4 µm˛ of course (assuming 0.16µm of contacts length)



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