Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

delay calculation in vhdl

Status
Not open for further replies.

Ponmalar21

Newbie level 4
Joined
Dec 18, 2014
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
29
How to generate random delay in the VHDL code??
 

How to generate random delay in the VHDL code??

First create a signal (for example - delay)
then pass values to this delay in process or where ever u need to pass


Code VHDL - [expand]
1
2
3
4
5
6
7
signal delay;
delay <= "011"
if delay /= "00" then
   delay <= delay - 1;
else
   delay <= "111";
end if;

 
Last edited by a moderator:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top