32Hz stable discrete square wave oscillator, how to?

BradtheRad said:

Do you have mains AC in the vicinity? Here's an idea. Tap into that. It will give you stable 50 or 60 Hz. Then divide by 2 through a flip flop.

You probably do not need to connect directly to mains. It should be possible to pick up mains hum in appliances several feet away. The right length, or shape, of antenna might help. Amplify the signal. Divide by 2 or 3 as you desire.

Click to expand...

No, that is not a good idea. AC mains, at least in Greece is not accurate to 50Hz, I do not know what is the case in other countries.

- - - Updated - - -

betwixt said:

For example if 32Hz was the reference producing 1MHz, 32.1Hz would produce 0.1Hz error in the 1MHZ, in other words the error is not multiplied.
Brian.

Click to expand...

That is exactly what I considered.

- - - Updated - - -

betwixt said:

Actually not necessarily true in the case of 'Huff n Puff', the lock range depends on the available control voltage range and it's tuning coefficient. In fact the biggest problem with this kind of control mechanism is difficulty changing the frequency and re-locking again. I note the kit mentioned a few posts back uses a variable time constant to allow rapid tuning with the stabilizer catching up only after the tuning stops.
Brian.

Click to expand...

In fact, the design posted is a slow puff n huff stabilizer.
It will have difficulty in stabilizing in higher frequencies.
The cure is the Fast version of it, which uses a shift register.
It is only the simplicity of the slow version that makes it interesting, a flip flop and a reference frequency.
The fast version used a sipo shift register which includes many flip flops.

I see a possibility of making a discrete slow version and the major problem is the reference clock.

It isn't quite the same as a PLL, the idea behind 'huff n puff' is it locks to increments of the reference rather than multiples of it. If I remember back to the original design proposal in Radcom magazine in the early 70's it used a 1MHz XTAL reference and had a 1 second time constant in the VCO filter (1M Ohm and 1uF I think). The stability is related to the reference but only in so far as an error in one may be duplicated in the other. For example if 32Hz was the reference producing 1MHz, 32.1Hz would produce 0.1Hz error in the 1MHZ, in other words the error is not multiplied.

Click to expand...

Sorry I don't get the meaning of "locking to increment". Presumed the 32 Hz is your only frequency reference and a 1MHz oscillator is somehow locked to this reference. Then the reference drifts e.g. by 0.1 ppm, won't the 1 MHz change by 0.1 ppm, too? So the absolute drift of the 1 MHz VCO is larger by a factor of 31250.

To actually "lock to the increment", there must be a second high frequency reference so that fvco = fref1 +/-k*fref2. fref2 drift will be still multiplied by factor k.

I might be overlooking something important. In this case I would appreciate an explanation in terms of commonly understood RF technique.

FvM said:

Sorry I don't get the meaning of "locking to increment". Presumed the 32 Hz is your only frequency reference and a 1MHz oscillator is somehow locked to this reference. Then the reference drifts e.g. by 0.1 ppm, won't the 1 MHz change by 0.1 ppm, too? So the absolute drift of the 1 MHz VCO is larger by a factor of 31250.

To actually "lock to the increment", there must be a second high frequency reference so that fvco = fref1 +/-k*fref2. fref2 drift will be still multiplied by factor k.

I might be overlooking something important. In this case I would appreciate an explanation in terms of commonly understood RF technique.

Click to expand...

This may be helpfull to you http://www.hanssummers.com/images/stories/library/qexfeb96.pdf It describes the slow puff n huff technique.

This may be helpfull to you **broken link removed** It describes the slow puff n huff technique.

Click to expand...

Essentially a PLL.

Not quite a PLL. The principle is more like a modulo divider with a result less than half the modulus or more than half the modulus deciding whether a positive or negative going ramp is applied to the control voltage. This is in contrast with a PLL where the control voltage is proportional to the phase difference between reference and input signals. It allows a lock condition at any multiple of the reference without changing the division ratio.

Brian.

Yes, I see. It's a different phase detector, allowing arbitrary frequency ratios. But as long as it's locked to a multiple of the reference, the frequency stability behaves similar to a regular rational PLL with fixed N and M.

"For example if 32Hz was the reference producing 1MHz, 32.1Hz would produce 0.1Hz error in the 1MHZ, in other words the error is not multiplied."

So is the error multiplied or not?
I am confused by the posts.

In general, the error is multiplied.

But the question itself isn't clear.

For 32 Hz reference, the VCO can lock to exactly 1 MHz, which is the 31250-fold
For a 32.1 Hz reference, the VCO might lock to nearest 1.0000113 MHz, the 31153-fold, you could say the error is only 11.3 Hz

However, if the VCO locks initially to 32 Hz reference which drifts slowly to 32.1 Hz, the VCO will drift by the 31250 fold, error is 3.125 kHz.

So about which case are you asking?

FvM said:

In general, the error is multiplied.

But the question itself isn't clear.

For 32 Hz reference, the VCO can lock to exactly 1 MHz, which is the 31250-fold
For a 32.1 Hz reference, the VCO might lock to nearest 1.0000113 MHz, the 31153-fold, you could say the error is only 11.3 Hz

However, if the VCO locks initially to 32 Hz reference which drifts slowly to 32.1 Hz, the VCO will drift by the 31250 fold, error is 3.125 kHz.

So about which case are you asking?

Click to expand...

All right, that is very clear, thank you