+ Post New Thread
Results 1 to 10 of 10
  1. #1
    Full Member level 3
    Points: 1,560, Level: 9

    Join Date
    Dec 2014
    Posts
    172
    Helped
    3 / 3
    Points
    1,560
    Level
    9

    Why do we fix set up violations in pre CTS stage and hold violations after CTS?

    Why do we fix set up violations in pre CTS stage and hold violations after CTS?

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 2
    Points: 3,454, Level: 13

    Join Date
    Apr 2011
    Location
    India
    Posts
    552
    Helped
    126 / 126
    Points
    3,454
    Level
    13

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    Setup violations are sometimes fixed by making changes to the logic. This can only be done preCTS. Hold violations are fixed by adding buffers to the data path. This is usually done postCTS. CTS itself leads to many hold violations.


    1 members found this post helpful.

  3. #3
    Full Member level 3
    Points: 1,560, Level: 9

    Join Date
    Dec 2014
    Posts
    172
    Helped
    3 / 3
    Points
    1,560
    Level
    9

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    Changes in logic may fix hold violations too, right?
    Suppose we have hold violations prior to the CTS stage itself. Then when should we try to fix it? After CTS or before CTS?



  4. #4
    Advanced Member level 2
    Points: 3,454, Level: 13

    Join Date
    Apr 2011
    Location
    India
    Posts
    552
    Helped
    126 / 126
    Points
    3,454
    Level
    13

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    Logic changes cannot fix hold violations.(But logic changes can solve setup violations e.g. pipelining..)
    You will get a true status of hold results only after CTS. So it is better we complete CTS and then look at hold results.


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  5. #5
    Member level 1
    Points: 643, Level: 5

    Join Date
    Nov 2014
    Location
    Trivandrum, Kerala
    Posts
    39
    Helped
    2 / 2
    Points
    643
    Level
    5

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    Quote Originally Posted by sharath666 View Post
    Logic changes cannot fix hold violations.(But logic changes can solve setup violations e.g. pipelining..)
    You will get a true status of hold results only after CTS. So it is better we complete CTS and then look at hold results.
    but there is chances for postCTS hold fix to violate setup, right?
    what we do for such situation?


    1 members found this post helpful.

  6. #6
    Advanced Member level 2
    Points: 3,454, Level: 13

    Join Date
    Apr 2011
    Location
    India
    Posts
    552
    Helped
    126 / 126
    Points
    3,454
    Level
    13

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    Usually we never come across such a situation. But we may use different cells to overcome it.


    1 members found this post helpful.

  7. #7
    Full Member level 3
    Points: 1,560, Level: 9

    Join Date
    Dec 2014
    Posts
    172
    Helped
    3 / 3
    Points
    1,560
    Level
    9

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    @sharath: I didn't get why logic changes cannot fix hold violations, but set up violations!! Can you explain in detail please?

    The set up time equation is expressed as
    Tclk>Tcq+Tcomb+Tsetup+Tskew

    whereas the hold time equation is expressed as
    Thold+Tskew<Tcq+Tcomb

    So, if logic changes make any effect on set up time, it should make some effect on hold time too, right??



  8. #8
    Advanced Member level 2
    Points: 3,454, Level: 13

    Join Date
    Apr 2011
    Location
    India
    Posts
    552
    Helped
    126 / 126
    Points
    3,454
    Level
    13

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    Ok. Assume u have setup violations in your design. You have to resolve it by reducing Tcomb. So 2 options available to u are pipelining and say retiming. Pipelining involves logic changes where you add registers to your RTL (logic changes)
    Asume Tskew is 0 for simplicity..
    If you have hold violations it means you have to push your data further ahead. You can do that by increasing TComb. The easiest way to do that is to add buffers in the data path. With this you can get incremental and precise control over the delay. If you want to do logic changes to solve this problem, what logic will you add in the data path. Any logic changes proposed will only complicate your problems.


    2 members found this post helpful.

  9. #9
    Full Member level 3
    Points: 1,560, Level: 9

    Join Date
    Dec 2014
    Posts
    172
    Helped
    3 / 3
    Points
    1,560
    Level
    9

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    That was a wonderful explanation. Thanks Sharath. :)



    •   AltAdvertisement

        
       

  10. #10
    Member level 1
    Points: 643, Level: 5

    Join Date
    Nov 2014
    Location
    Trivandrum, Kerala
    Posts
    39
    Helped
    2 / 2
    Points
    643
    Level
    5

    Re: Why do we fix set up violations in pre CTS stage and hold violations after post C

    OK. that's a good briefing about setup and hold, Thanks Sharath.
    Last edited by kannanunni; 27th May 2015 at 07:17.



--[[ ]]--