QMA
Member level 4
Dear all
I am new to verilog. I have written the below code for full adder using two half adders. it is giving me syntax error
Code for full adder
Code for half adder
I am new to verilog. I have written the below code for full adder using two half adders. it is giving me syntax error
. The code for half adder is given at the end. Please help me in this regard.
Code for full adder
Code:
module Full_adder(
input cin,
input a,
input b,
output cout,
output sum
);
wire w1,w2,w3;
H_adder h1(.w2(s),
.w1(c),
.a(a),
.b(b)
);
H_adder h2(.sum(s),
.w3(c),
.w2(w2),
.cin(cin));
or (cout,w1,w3);
endmoduleCode for half adder
Code:
module H_adder(
input a,
input b,
output s,
output c
);
assign s = a^b;
assign c = a&b;
endmodule