DC-DC converter isolation, questions from a newbie.

you can set your turns ratio to give you what ever duty cycle you want at min input voltage, max vout. Then see how small the duty goes for the min vout. If the on time is too small, then you may need a secondary regulator, say a buck like you said. obviously lower switching frequency means more duty cycle range at low duty cycle end of things. If your fet on time is the same time as the fet transition time then that's not good.
Double ended single ended, I don't really know, but think full bridge is double, 2TFC is single.

I see, so far I have focused completely on the flyback topology and gotten used to the inductor-transformer idea but the forward topology uses a real transformer.

I was about to implement my first flyback prototype before you recomended and changed my mind to go for a forward design and I have jet to wind my transformer so the change is not a big one, perhaps adjust the PWM control circuit(but maybe not) and then just add a diode and inductor on the outputs.

I have to do some more reading before I implement the forward design though, I need a better understanding about the transformer and output filter requirements.

One other thing though, the current levels. Can one trust the calculated current peaks or may them differ in real world much?
I think it is obvious that the may differ but is the calculations done anywhere close to realistic?

I don't know what is going on but while using the supplied LTspice circuits the simulation time has become to long to be of any use, but it only concerns circuits that I have altered.
While I managed to get the simulation going again it now never finishes because of an error:

Analysis: Time step too small; time = 4,01817e-005, timestep =
1,25e-019: trouble with rfx10tf6s-instance d2

rfx10tf6s is the rectifier diodes used to rectify the mains voltage and no matter which I choose they are mentioned in the error message, as to what time steps it referees to I don't know but I suppose I will have to search for help through the LTspice google group.

It's annoying anyway.

I still have not gone through all the files but I am sure that as I learn how to use LTspice they will be of very good use, thank you again.

Regards

A simulator can run into convergence problems when you put diodes and inductors and capacitors adjacent.

It might help if you install high-ohm resistors (a) across different components, or (b) from different nodes to the supply rails.

Also try installing low-ohm resistors inline with capacitors.

Ok, I shall try that.
Although first I solved it jet the simulation runs much slower than other has, and my current circuit which is a simplified version without the AC mains part and without a IR2110 model does display a situation which in the past has driven me nuts.

I configure a transient analysis but when I press run no new window opens but I can see in the bottom of the window that something is taking place but it does not look like when a ordinary simulation takes place.
I don't know how I manage to miss-read thing so often but there is a obvious setting for minimum step time which I must have read 20 times as something else-

I would like to check my progress with you all, my calculated output inductor is HUGH in my mind at least.

I am using a ETD34 core and my calculated minimum primary turns is 436,4, which if made 437 together with the secondary turns = 182 fulfills the equation Npri/Nsec < 2,4, or a turns ratio of 0,4163
2,4 comes from (Vin_min/Vout)*D = (269V/56V)*0,5.

I have used:
Vin_min = 269Vdc
Vin_max = 339Vdc
Vout = 55V
Iout_max = 5A
Iout_min = 10% of max or 5A
Δi_Lo = 1A (ripple current peak to peak must be less than this)
D_max = 0,5

And I have calculated minimum output inductance with two different equations and one says Lo > 1684µH
and another says Lo > 2927µH
To get those kind of values with a inductor that can handle 5A does not sound reasonable to me.
Is it?

To get the minimum primary turns I used a value for Bsat = 0,2T but if I as told by a app note use 0,3T the turns falls from 436,4 to 290,9.
As I interpret the ETD34 datasheet 200mT is to be used although the app note tilling me to use 300mT in concerning the same core.


AHA, I calculated as if I had a core that could output 275W but a ETD34 core would not be able to handle over 97W(according to some literature, and that is before I de-rate it according to topology used)

Although the output power does not seam to concern the transformer turns and so that mistake does not seem to matter so far anyway.

Regards

ref the ltspice, simulator problems....when you hit the running man icon, and you have to choose the simulation time etc, tick the box titled "skip initial operating point calculation", and that may well help. (its at the bottom, that may not be the exact phrase)
Also, if it keeps going bad, click the hammer icon, then go to the spice tab,...select a different solver......any, just change it....often the "alternate 2" solver works well. , but sometimes "normal 1" is best.
Be sure to have selected an actual diode or fet etc model, as it wont like it if you don't.
Remember to delete the big raw files after you've finished simulating, else your hard drive will get full.
If you still have trouble, the yahoo groups ltspice group will solve it for you, just upload it there and Helmut Sennewald will adjust it and enable it to run for you

- - - Updated - - -

is there anything in here of relevance, its smps stuff plus simualtions...aaahh....I just tried twice to upload 35MB and it wont take it...the thing says it can take up to 1ooMB...ill try and send it later

- - - Updated - - -

here it is...

- - - Updated - - -

I cant understand why it wont upload, its only 35mb zip file

- - - Updated - - -

ok done it now..

David_ said:

And I have calculated minimum output inductance with two different equations and one says Lo > 1684µH
and another says Lo > 2927µH
To get those kind of values with a inductor that can handle 5A does not sound reasonable to me.
Is it?

Click to expand...

This is a reasonable range of inductor values, to obtain your low current ripple spec.

You might run a 2mH inductor at 25kHz (an easy-to-handle frequency). Or you might run a 1mH inductor at 40 kHz. Etc.

The above is what I find by trying a simple simulation. Coil current is 6.2A peak, 5.1A trough. Duty cycle is 37 percent, with a power supply at 170 VDC.

so you are using 2TFC.
At min vin, max pout, go for duty cycle of 0.39....no more than that else your txfmr leakage could mess up for you.
I treat it as a buck converter, put in the duty cycle, then calculate what "imaginary vin" you would want if it was a buck...then put in the transformer, with suitable turns ratio to GIVE you that "imaginary vin" from the minimum actual vin.

So you have vout=55v
Say you pick D = 0.39 at min vin
Then you need "imaginary vin" = 141v (55/0.39)

So your actual vin min is 269v
to get 141v from that you need a txfmr with turns ratio = np/ns = 269/141..........but because of leakage L, make the secondary turns a bit more, so go for np/ns = 269/130, say.

tHE sizing of your output L depends on
1...How much ripple current pkpk you are preaperd to tolerate in it, and the switching frequency.
However, you do not state fsw
Remember the equations of use to you are the equations of a trapezoid, cuzz all hard switchers have trapezoid shaped waveforms.....there are only three, and you can find them here..courtesy of brad suppanz and oocities

https://www.oocities.org/capecanaveral/lab/9643/rms.htm

here is design spreadsheet for your 2tfc...but note this is not power factor corrected, so you mains peak currents will be very large.
You said vin = 269 to 339v so I assumed you were skipping the pfc stage for now

Yes I did remove any PFC circuit but now I feel as if such a circuit would make the design of the DC-DC converter simpler through the constant(ish?) input voltage from the PFC stage.
Am I right in thinking that a PFC stage could take care of the power factor issue as well as receiving a varying voltage and producing a stable voltage?

My mains rectified should be 269V to 339V and it would be nicer if I could get a lets say 400V from a PFC stage, I am continually reading about PFC's now but I can't jet answer this and the answer sort of decides for me if I will bother with the PFC stage at this time.

I will need some time to even know what it is you have posted for material for me but I sure look forward to finding out.

Regards

yes, the pfc stage will give you a more stable output, but unless you use loads of output caps after the pfc, then you will get about 20 pktopk ripple, depending on capaciatance, but that's an improvemenet anyway. I have sent you sims of pfc stage with lt1248 chip in previous post. With 250w, and no pfc, your mains input current would be very peaky indeed...so pfc is better really for you

Hello.

I vaguely remember reading about the PFC frequency and that it is preferred to have a higher PFC frequency than the following DC-DC Converter frequency but more recently I have come to the conclusion that it would perhaps be beneficial if the two operating frequency's where synchronized, now I can't justify the following but I read that if I use two converters as in a PFC followed by forward converter and design them both to run at 25kHz all on there own that might create noise by some process involving two ≈ 25kHz frequency's.
I can't resolve how and why but as I write this I thought "might I use LTspice or Matlab to simulate such a close frequency interaction, I can't say more than I think I really should be able to quite swiftly make some use of my software resources but I often find my self in this same situation.
I think that it should be a quite obvious way for me to research things like the above converter frequency interaction but I have no clue of where to start even, so I am going to write out my first thoughts, so lets see how that goes.

I have two converters that follows each other, noise would probably be irradiated from the gate drive traces of the PCB as well as there would be noise in the wave form of the converter output DC voltage, if that is true(by the way I am aware that this particular case might not be relevant since it is about 25kHz clocks, and as such the EMI problem might not have any larger system impact...?) then ether I

• use LTspice to implement a CCM PFC regulator followed by a Buck converter and observe the output voltage in two cases, one where the frequency's is the exact same one and the other where one is 25*0,97 kHz and the other 25*1,03 kHz or

• I use Matlab to synthesize sine-wave signals of different frequency's and perhaps I make a DC signal and then add a ~25kHz sine-wave component and see where that leads me.

I have recently begun to learn about Fourier Series and FFT though I have had a hard time with the math so I have not gotten to the FFT jet, I mean I can follow the math for the most part but how do you integrate numbers and how does the sigma sign work exactly, but I have thought I will buy two of the math tutors from MathTutorDVD.com
One to learn algebra and one with something that should help in the FFT area.

But my reasoning so far, am I on the right track in any way at all. Note that this level of research might not be needed but I need to learn how to do stuff, I can work with both LTspice and Matlab as software but how to solve real circuit problems and how to solve anything more complex is not something I have managed to do, I will open another thread about my latest tries with signal processing.

Since this became so long lets sum up what I am asking:
For one thing I simply want to know if the PFC frequency should be higher than or synchronized to the forward's oscillator?

Everything else is my attempt at analyzing the question of how to different oscillator frequency's will interact with each other and that does not really have anything to do directly with this subject but I have failed completely on my own so I would really appreciate if anyone had anything to say about this or adjust my heading if I am going the wrong way.

Regards

Oh wait, I forgot. I have started looking into UCC28180, a CCM PFC controller in a SO8 package that has a really small and simple external which supports the usual protection features. If anyone does not point out some disadvantage or other down side to this implementation then I think I will stay with it and as soon as I have calculated the component values I will consider the PFC stage complete apart from the oscillator uncertainty.

For one thing I simply want to know if the PFC frequency should be higher than or synchronized to the forward's oscillator?

Click to expand...

With god PCB layout, you shouldn't need to worry about "beating" between the pfc stage and the other converter. After all, there is a big capacitor between them too.

sOmestimes, in order to reduce ripple current in the pfc output capacitor, you get chips which synchronize the pfc to the downstream converter so that when the pfc pushes current out, that coincides with the downstream converter sucking current in, so you get less ripple current in the cpacacitor between them. But few people seem to bother with that.
There is a power integrations application note about what you are saying about "beating" though, or rather the incidence of two switching edges (one from each converter) being close to each other.....I think there chip does indeed synchronize them for the very problem that you speak of. I think its one of the power integrations chips that does pfc and llc resonanant converter from one chip.

..interestingly that Power integrtations chip which coordinated both the PFC stage and the LLC stage looks to have gone off the market, so looks like any interaction between PFC and SMPS downstream is just not important. It was one of the "Hiper" family.
I hope you will not feel inhibited, since as we know, working engineers in companies very often are totally short of ideas, but just get on and do it. I went into a very large company once (you may well have heard of it), and a large team of engineers was trying to design ~20W offline flybacks......they were getting too much loss in the RCD primary snubber and couldn't work out why..Then after a few weeks, they were told about the fact that they weren't interleaving their transformer windings. To think that "real" engineers didn't know this.

One of their senior engineers came up to me with a huge tome of a physics book on magnetics, telling me it was what he used to great success when working at GE, and told me he was going to work it out......I then showed him application note 18 from power integrations, and he never looked back. Never saw him with that physics book again.

You do have to worry about sub-harmonic resonances from the CM line filter , especially with low input and high load.