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MOS Parasitic Capacitance Calculation in Cadence Spectre

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I want to design a circuit in which parasitic capacitors are very important, and I'm trying to derive some formula which necessitates calculating these capacitors by a specific equation (and not just simulating and checking their value every time). Is there any such equation? Specially for Cds.
 

As long as you don't know the connection lengths between the individual devices in layout, you can't even make a reasonable estimation.

If you can draft a schematic which reasonably would mirror the expected lengths of the future layout connections, you could measure the connection lengths and calculate their anticipated mean values on a Cp/µm (and, if necessary Rp/µm) basis of the used process.

You can get these figures e.g. from the **broken link removed**; use the global wire values. Cap/length values do not depend too much on process size; for such a rough estimation you can use 0.2fF/µm.

This could result in a very, very rough estimation.

If you want, try this and compare with results from an extracted layout.
 
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