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What to check after logic synthesis?

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ivlsi

ivlsi

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Hi All,

What should I check after logic synthesis?

As for me, here is the list:
1) Timing Warnings (negative slacks)
2) Gate Count

What am I missing?

Thank you!
 

Power.
ATPG fault coverage.
Logical equivalence of RTL to netlist.
Missing timing constraints.
 
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    ivlsi

    ivlsi

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