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Behavioral and structural modelling in verilog

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tv123

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Will the power consumption for a design done in behavioral verilog and structural verilog be same?
 

If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.
 

sharath666 said:
If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.
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What if both refers to same logic, say , if both refer to a d flipflop?
 

Then it should be the same as post synthesis netlist will be the same.
 
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