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  1. #1
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    Behavioral and structural modelling in verilog

    Will the power consumption for a design done in behavioral verilog and structural verilog be same?

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  2. #2
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    Re: Behavioral and structural modelling in verilog

    If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.



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  3. #3
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    Re: Behavioral and structural modelling in verilog

    Quote Originally Posted by sharath666 View Post
    If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.
    What if both refers to same logic, say , if both refer to a d flipflop?



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  4. #4
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    Re: Behavioral and structural modelling in verilog

    Then it should be the same as post synthesis netlist will be the same.


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