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    Minimum L2 Density in UMC65 design

    I am not able to resolve the following DRC error in a UMC65 design.
    L2.D Minimum L2 density cross full chip is 10%

    What is L2?

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  2. #2
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    Re: Minimum L2 Density in UMC65 design

    Quote Originally Posted by punu View Post
    I am not able to resolve the following DRC error in a UMC65 design.
    L2.D Minimum L2 density cross full chip is 10%

    What is L2?
    Hi,

    Maybe you can check this thread https://www.edaboard.com/thread95896.html



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  3. #3
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    Re: Minimum L2 Density in UMC65 design

    Quote Originally Posted by punu View Post
    What is L2?
    Find the layer in the LSW; the assignment to the layout can be found if you toggle it invisible - visible, s. here: LSW-description.pdf

    Or search your PDK docu for L2.



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