[SOLVED] RF Trace Width Issue

Hi,

after calculating the trace width for 50 Ohm impedance line, the width is 0.30 mm.

• There is no problem at traces but on QFN pins which have a limited spacing, could RF traces have a neck near to SMT pins without affecting too much to RF line impedance? So, RF traces fit in a proper way to avoid any DRC error.
• In case there's no option to reduce the line width in this case, if I maintain the current line width, will the nearest pins (VDD) to RF ones affect to RF signal integrity?
• Does any rule of thumb to route the RF trace on the PCB?
• What is the common clearance between the RF trace and ground plate?

Regards.

To achieve 0.3 mm trace width for 50 ohms on FR4, the substrate height must be about 180 µm. Is it so?

More usually, the feasible line width is far below that required for 50 ohms. So it's unavoidable to reduce tracks near a QFN pin. Consider that the bond wire inside the IC package neither continuous 50 ohms impedance.

Traces shorter than λ/10 should be imagined as a small inductance rather than a transmission line. They have a certain effect on the circuit behaviour, but can be well compensated in overall impedance matching.

To keep a trace impedance near the chip, which would be meaningful in the high GHz range, you can also combine microstrip with coplanar design principles. In the present case, there seem to be a differential pair, so adjusting the soacing between both traces gives another means to achieve a certain differential impedance.

The Vdd + signal integrity questions sounds somehow absurd. Both nodes are entering the chip on neighbour bondpads and Vdd will be surely bypassed very near the chip so that it can (and must) be treated as ground in impedance calculations.

Hi FvM,

thanks for your answer.

Please, let me comment some doubts I have about.

lambda = c / (f * sqrt(Er)) -> lambda = 0.0959 m
c = 3*10^8 m/s
f =2.4 GHz
Er = 4.5 (FR4)

Then:
length -> lambda / 10 = 5.959 mm

So, if I only do a simple calculation, even if it is no precise, there is:

Characteristic Impedance is almost 50 Ohm.

Then, if I do the calculations dividing into two parts the line (I know this is not the right manner, but it is the way I read about).
1. Coupled MSLine (first stretch).

2. MSLine (second stretch).

It seems to be near 50 Ohm too.

Although it is still pending to adjust matching network component values, I think 0.3 mm width could be suitable for maintaining the right impedance.

That's what I'm asking about the trace width at IC pads.

Please, if I'm wrong I wonder you to help with the steps to follow, so I can fix my design.

Regards.

yolco said:

Then:
length -> lambda / 10 = 5.959 mm

Click to expand...

This lambda/10 is important because impedance mismatch in shorter lines will have only small effect. Line width isn't critical for these electricalyl short lines. You can design them for 50 Ohm, but it is not critical.

yolco said:

1. Coupled MSLine (first stretch).
View attachment 116587

Click to expand...

You have plotted the even mode impedance (by mistake?) I expect that your lines have a differential signal, so that we are looking for the odd mode impedance.

But again, if this line segment is short, don't worry!

yolco said:

Although it is still pending to adjust matching network component values, I think 0.3 mm width could be suitable for maintaining the right impedance.

Click to expand...

As you have shown for the MS line, 0.3mm is close to 50 Ohm. Looks perfectly fine.

Tip: There is no repeat that calculation for your two different length, because the line impedance is independent of the length parameter. The length parameter is only used to calculate the electrical length (phase).

Thanks a lot volker@muehlhaus!

The total length is 6.7 mm, so I'm a bit over lambda/10 (5.96 mm), but under lambda/8 (7.45 mm), so I playing in a dangerous zone, for not taking into consideration the MS line length.

If I change the mode to odd, the width for 50 Ohm impedance decreases till 0.263 mm.
Although the IC has two RF signals (RF_P & RF_N), the path is a single one, there is only one 'wire' for RF signal.

• Do I have to consider the first stretch as if signal was a differential one? Do I have to change the width for the first stretch?
• Or as the length is under the limits, could I maintain the same width for both stretchs?
• Which would the right spacing, w/2?

Regards.

For a differential signal, you should determine differential and common mode impedance directly. The calculation is supported by many tools.

yolco said:

Although the IC has two RF signals (RF_P & RF_N), the path is a single one, there is only one 'wire' for RF signal.

Click to expand...

I don't understand what you mean. For the differential output, we have two lines over ground. If the lines have a large distance and don't couple, we have 50 Ohm on each output (RF_P to GND, RF_N to GND) resulting in 100 Ohm differential impedance (RF_P to RF_N). The lines are then individually sized for 50 Ohm per microstrip line, because they don't couple and Zodd = Zline, which is the same thing as Zdiff = 2 * Zline.

If the lines are closely spaced, we start to see an effect on differential impedance and then we want to design for Zodd = 50 Ohm (Zdiff = 100 Ohm differential impedance).

yolco said:

[*]Do I have to consider the first stretch as if signal was a differential one? Do I have to change the width for the first stretch?

Click to expand...

If Zodd is near the single line impedance, it means that both lines don't couple and you don't need to worry. And because the length is short anyway, I would do what makes sense for layout. Electrically the effect is to small to worry.

yolco said:

[*]Or as the length is under the limits, could I maintain the same width for both stretchs?

Click to expand...

Yes, this is what I would do, if layout permits. Otherwise do whatever works for layout design rules.

yolco said:

[*]Which would the right spacing, w/2?

Click to expand...

Theoretically as much spacing as possible, if the line width is calculated for a single line. But again ... don't worry, it is not so very critical.

Hi,

thanks for your answers!

Layout allows me to maintain the same width, but Zodd is 46 Ohm which I think is a bit far away from single line impedance.
As both lines are closely spaced, I'm going to modify the width line for the first stretch (Coupled MS Line) to 0.26 mm (Zodd = 50.3 Ohm), and maintain the second stretch width (single MS line) to 0.3 mm.

I'm trying to make my best effort to design this PCB, and also improving my knowledge on PCB design.

Kind regards!

Designing a PCB for a specific impedance without "impedance controlled" production can only roughly achieve the target value, particularly if regular FR4 is used. Impedance variations of +/-10 % relative to designed value should be considered as excellent result.