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how to assign values to wire in verilog

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badari259

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i know that initially it's value will be z. but this makes my mac unit not to add and accumulate. the adder is adding the multiplied result to the wire whose initial value is z. what should i do? please help me. thanks.
 

badari259 said:
i know that initially it's value will be z. but this makes my mac unit not to add and accumulate. the adder is adding the multiplied result to the wire whose initial value is z. what should i do? please help me. thanks.
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You should show the code for your mac unit.

Not sure if you should actually be using an assign, but since you ask for it and show no code to base better advice on ... https://www.asic-world.com/verilog/synthesis3.html
 

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