advantage of more number of metal layers

wat is the advantage of using more number of metal layers wen going to deep sub micron or submicron tech? does this increase the flexibility of routing or does this minimise the emi between power and ground?

viswa said:

wat is the advantage of using more number of metal layers wen going to deep sub micron or submicron tech? does this increase the flexibility of routing or does this minimise the emi between power and ground?

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For standard-cell digital-design (Verilog/VHDL), more interconnect layers loosely translate into "higher utilization" (gate-density.) Like you said, theadditional layers give the router-tool more "degrees of freedom" to connect gates to each other. As a side-effect, due to tighter packing of the gates, a circuit's critical-path may be shortened (and therefore achieve a higher max clock-frequency.)

The # interconnect layers affects manufacturing cost. Each interconnect layer requires a number of processing steps, so a chip with 8LM requires a larger mask-set and more wafer processing steps to complete. This translates into higher production cost, and potentially lower yield (due to the defecting per metal-layer.)

I don't know about the electromigration...