Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why is 'ddiscrete' not allowed in verilog-AMS simulation?

Status
Not open for further replies.
R

ruwan2

Member level 5
Joined
Nov 29, 2011
Messages
90
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,141
Hi,

I see the below code from verilog-AMS reference book.




`include "disciplines.vams"
module a2d(dnet1a, anet);
input dnet1a;
output anet;
wire dnet1a;
ddiscrete dnet1a;
electrical anet;
real avar;

analog begin
if (dnet1a === 1'b1)
avar = 5;
else if (dnet1a === 1'bx)
avar = avar; // hold value
else if (dnet1a === 1'b0)
avar = 0;
else if (dnet1a === 1'bz)
avar = 2.5; // high impedance - float value
V(anet) <+ avar;
end
endmodule
Click to expand...

When I run simulation of it in SMASH 6.3.0, it has error message:

ERROR: syntax error near discrete
C:\Users\rj\Documents\SMASH_Verilog_AMS_prj\one_bit_dac.vams(27): discrete dnet1a;
Click to expand...

I have included `include "disciplines.vams". And that file has ddiscrete definition:

discipline logic
domain discrete;
enddiscipline

discipline ddiscrete
domain discrete;
enddiscipline
Click to expand...


What is a solution for this? The AMS standard, or the EDA software?


Thanks,
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top