Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help Need: Please help me to understand this code

Status
Not open for further replies.
T

tokwatbaboy

Newbie level 6
Joined
Sep 5, 2011
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Singapore
Activity points
1,353
Not a RTL coder but I need to understand this piece of code:

finalGater = scanEn ? testModeEn: ~scanEn ? funcMode : 1'hx;

what does it means? any sample code/syntax I can use as reference?

thanks!
 

tokwatbaboy said:
finalGater = scanEn ? testModeEn: ~scanEn ? funcMode : 1'hx;
Click to expand...
And regarding code readability, personally I'd write that like so:
Code SystemVerilog - [expand]
1

finalGater = scanEn ? testModeEn : (~scanEn ? funcMode : 1'hx);

That way it's easier to see how the ~scanEn ? funcMode : 1'hx part of the expression is evaluated. Not just for yourself, but also for future victims. Even if that future victim is future you. ;)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top