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20th March 2015, 20:29 #1
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logic to generate variable frequency output.
hello all, recently i am working on a project that is variable frequency drive. i am using pic microcontroller for the programming purpose.in the programming section, i have one sine look up table and have to generate various such tables during run time(each table corresponds to a particular frequency).
now i want a logic that can generate various lookup tables for me from one table during run time. for sample purpose, i am posting to tables here, one for 50hz output frequency and other for 10hz output frequency. if anyone can help, kindly reply.
fiftyyy=[0, 2, 3, 5, 7, 8, 10, 11, 13, 15, 16, 17, 19, 20, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31, 32, 33, 33, 33, 34, 34, 34, 34, 34, 34, 34, 33, 33, 33, 32, 31, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 20, 19, 17, 16, 15, 13, 11, 10, 8, 7, 5, 3, 2];
ten=[0, 9, 17, 26, 34, 42, 51, 59, 67, 74, 82, 89, 97, 104, 110, 117, 123, 129, 135, 140, 145, 149, 153, 157, 161, 164, 167, 169, 171, 172, 173, 174, 174, 174, 173, 172, 171, 169, 167, 164, 161, 157, 153, 149, 145, 140, 135, 129, 123, 117, 110, 104, 97, 89, 82, 74, 67, 59, 51, 42, 34, 26, 17, 9];
i have fifty such tables but i just can use one table as static memory of the program, all other tables have t0 be generated during run time. kindly help if u can.

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20th March 2015, 20:44 #2
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Re: logic to generate variable frequency output.
Instead of generating different lookup tables during execution  what would make an expressive overhead on core processing  you could consider to simply change the sample frequency for the PWM, but using a single table.

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20th March 2015, 23:03 #3
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Re: logic to generate variable frequency output.
could you please elaborate? i cant get ur point.

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21st March 2015, 01:54 #4
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Re: logic to generate variable frequency output.
Generate a sine table at run time is out of consideration, as this would require a significant amount of core calculation composed of several multiplication and division operations.
If instead this, you can use only one table hard coded, but now the duration of the PWM period no longer being predetermined as in the case above, but now being inversely proportional to the frequency of interest ( for example, a frequency doubled rate will have a sampling halved ), for each duty cycle, you would have to deal in the best case, with a scaling factor that could be reached by a simplest algebra, although needing at least 1 division operation.
Which uC are you using, 8bits, 16bits ?
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21st March 2015, 12:41 #5
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Re: logic to generate variable frequency output.
uc is 16 bit. 18f4431.
thank u for ur valuable suggestions. to vary frequency using a pic18f4431, u have to control two FSRs
1) PR2 register (i have controlled it using adc and simple algebric equation, any value can be generating by reading output of an adc)
2) duty cycle register, ( ccpr1 ) for which lookup table should be generated (i am stuck on it).
now i cant use only one table by simply by varying sampling frequency.
e.g for 50 hz, pr2=155 and sine table have highest value of 140, which is the on time of one pwm cycle.
and for 10hz , pr2=240 and highest value in table is 216.
now suggest what should i do, i am badly stuck in it.

21st March 2015, 12:55 #6
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Re: logic to generate variable frequency output.

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21st March 2015, 20:25 #7
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Re: logic to generate variable frequency output.
well, at the moment, i am tyring to map frequency vs adc value as:
05v > 1050Hz
obiviously, if i cant found a way to do that, i will rely on limited number of sine tables, may be by a resolution of 5hz, thus a total of 9 tables, which i can define in the static memory of the program. as i have to complete the project as it is my final year project in BE Electrical Engineering, if i dont complete it, my degree will be stuck.
but will not be a variable frequency drive, talking in real world :)
kindly help in any manner if u can :)

21st March 2015, 21:40 #8
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Re: logic to generate variable frequency output.
I believe that the solution to the problem was always here in front to our eyes since the beginning. You can generate a set of 9 sine tables having all the 64 dutycycles for the CCPR1 register, each one for each frequency, and another set of 9 tables to store the 2 values to be loaded to the PR2 register, that´s not right ?
Note that the above code would theoretically require a memory of somewhat near to 9*(64+2)=600 words of uC, but if you consider that the table has a clear symmetry, could even reduce to half through a simple up/down control logic. what do you think to make a quick test, building a code even with fake values ?
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22nd March 2015, 07:33 #9
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Re: logic to generate variable frequency output.
i have found a relation between all the tables, actually, its a constant factor that shoud be multiplied with the 50hz table. however on software level, now i am unable to vary the frequencies through 10hz to 20 hz. above 20hz, i am not getting the results. so now i am trying to explore the reason.
i will try this and get back to you.

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22nd March 2015, 11:13 #10
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Re: logic to generate variable frequency output.
Ok your 50Hz table has 64 entries, so you are effectively sampling at 3200Hz?
Store one table, the 50Hz one will do.
You then have a 16 bit variable, call it 'phase' initialized to zero, the upper 6 bits of which are used as the index into your table.
Finally, every time thru your 3200Hz loop you simply add a constant (depending on the desired frequency) to the value of phase and output whatever table entry the upper 6 bits point to.
Bigger tables make better sines at low frequency.
In sort of C:
Code:uint16_t phase = 0; while (1){ . phase += 0x400; // top 6 bits, so this should give 50Hz, 0x200 gives 25Hz, 0x800 gives 100Hz and so on. set_output (table[(phase >>10)]; . . . }
Regards, Dan.
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